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DAC38RF83IAAVR Datasheet(PDF) 78 Page - Texas Instruments |
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DAC38RF83IAAVR Datasheet(HTML) 78 Page - Texas Instruments |
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78 / 160 page  Table 7-43. Register Summary (continued) Address Reset Acronym Register Name Section 0x1D 0x0000 PHASE_NCOCD Phase offset for CD path NCO 7.5.24 0x1E-0x20 0x0000 FREQ_NCOAB Frequency for AB path NCO 7.5.25 0x21-0x23 0x0000 FREQ_NCOCD Frequency for CD path NCO 7.5.26 0x24 0x0010 SYSREF_CLKDIV SYSREF Use for Clock Divider 7.5.27 0x25 0x7700 SERDES_CLK Serdes Clock Control 7.5.28 0x26 0x0000 Reserved Reserved 0x27 0x1144 SYNCSEL1 Sync Source Selection 7.5.29 0x28 0x0000 SYNCSEL2 Sync Source Selection 7.5.30 0x29 0x0000 PAP_GAIN_AB PAP path AB Gain Attenuation Step 7.5.31 0x2A 0x0000 PAP_WAIT_AB PAP path AB Wait Time at Gain = 0 7.5.32 0x2B 0x0000 PAP_GAIN_CD PAP path CD Gain Attenuation Step 7.5.33 0x2C 0x0000 PAP_WAIT_CD PAP path CD Wait Time at Gain = 0 7.5.34 0x2D 0x1FFF PAP_CFG_AB PAP path AB Configuration 7.5.35 0x2E 0x1FFF PAP_CFG_CD PAP path CD Configuration 7.5.36 0x2F 0x0000 SPIDAC_TEST1 Configuration for DAC SPI Constant 7.5.37 0x30 0x0000 SPIDAC_TEST2 DAC SPI Constant 7.5.38 0x31 0x0000 Reserved Reserved 0x32 0x0400 GAINAB Gain for path AB 7.5.39 0x33 0x0400 GAINCD Gain for path CD 7.5.40 0x34-0x40 0x0000 Reserved Reserved 0x41 0x0000 JESD_ERR_CNT JESD Error Counter 7.5.41 0x42-0x45 0x0000 Reserved Reserved 0x46 0x0044 JESD_ID1 JESD ID 1 7.5.42 0x47 0x190A JESD_ID2 JESD ID 2 7.5.43 0x48 0x31C3 JESD_ID3 JESD ID 3 and Subclass 7.5.44 0x49 0x0000 Reserved Reserved 0x4A 0x0003 JESD_LN_EN JESD Lane Enable 7.5.45 0x4B 0x1300 JESD_RBD_F JESD RBD Buffer and Frame Octets 7.5.46 0x4C 0x1303 JESD_K_L JESD K and L Parameters 7.5.47 0x4D 0x0100 JESD_M_S JESD M and S Parameters 7.5.48 0x4E 0x0F4F JESD_N_HD_SCR JESD N, HD and SCR Parameters 7.5.49 0x4F 0x1CC1 JESD_MATCH JESD Character Match and Other 7.5.50 0x50 0x0000 JESD_LINK_CFG JESD Link Configuration Data 7.5.51 0x51 0x00FF JESD_SYNC_REQ JESD Sync Request 7.5.52 0x52 0x00FF JESD_ERR_OUT JESD Error Output 7.5.53 0x53 0x0100 JESD_ILA_CFG1 JESD Configuration Value used for ILA Check 7.5.54 0x54 0x8E60 JESD_ILA_CFG2 JESD Configuration Value used for ILA Check 7.5.55 0x55-0x5B 0x0000 Reserved Reserved 0x5C 0x0001 JESD_SYSR_MODE JESD SYSREF Mode 7.5.56 0x5D-0x5E 0x0000 Reserved Reserved 0x5F 0x0123 JESD_CROSSBAR1 JESD Crossbar Configuration 1 7.5.57 0x60 0x4567 JESD_CROSSBAR2 JESD Crossbar Configuration 2 7.5.58 0x61-0x63 0x0000 Reserved Reserved 0x64 0x0000 JESD_ALM_L0 JESD Alarms for Lane 0 7.5.59 0x65 0x0000 JESD_ ALM_L1 JESD Alarms for Lane 1 7.5.60 0x66 0x0000 JESD_ ALM_L2 JESD Alarms for Lane 2 7.5.61 0x67 0x0000 JESD_ALM_L3 JESD Alarms for Lane 3 7.5.62 0x68 0x0000 JESD_ALM_L4 JESD Alarms for Lane 4 7.5.63 DAC38RF80, DAC38RF83, DAC38RF84 DAC38RF85, DAC38RF90, DAC38RF93 SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023 www.ti.com 78 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 |
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