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DAC38RF83IAAVR Datasheet(PDF) 95 Page - Texas Instruments |
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DAC38RF83IAAVR Datasheet(HTML) 95 Page - Texas Instruments |
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95 / 160 page ![]() Table 7-64. CMIX Field Descriptions (continued) Bit Field Type Reset Description 3:0 CMIX_CD R/W 0x0 These bits turn on the different coarse mixing options. Combining the different options together can result in every possible n x Fs/8 [n=0->7]. Below is the valid programming table: cmix=(mem_fs8; mem_fs4; mem_fs2; mem_fsm4) 0000 : no mixing 0001 : -fs/4 0010 : fs/2 0100 : fs/4 1000 : fs/8 1100 : 3fs/8 1010 : 5fs/8 1110 : 7fs/8 7.5.22 Output Summation and Delay Register (address = 0x19) [reset = 0x0000] Figure 7-55. Output Summation and Delay Register (OUTSUM) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-65. OUTSUM Field Descriptions Bit Field Type Reset Description 15:12 OUTPUT_DELAY R/W 0x0 Delays the output to the DAC 0 to 15 clock cycles 11:4 Reserved R/W 0x00 Reserved 3:0 OUTSUM_SEL R/W 0x0 Selects the output summing functions. Each bit selects another sample to sum. Multiple bits can be selected. bit 0 = add the path AB sample bit 1 = add the path CD sample bit 2 = add adjacent DAC path AB sample bit 3 = add adjacent DAC path CD sample 7.5.23 NCO Phase Path AB Register (address = 0x1C) [reset = 0x0000] Figure 7-56. NCO Phase Path AB Register (PHASE_NCOAB) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 0 0 1 1 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset www.ti.com DAC38RF80, DAC38RF83, DAC38RF84 DAC38RF85, DAC38RF90, DAC38RF93 SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 95 Product Folder Links: DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 |
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