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DM505LRBABFR Datasheet(PDF) 96 Page - Texas Instruments |
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DM505LRBABFR Datasheet(HTML) 96 Page - Texas Instruments |
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96 / 295 page  96 DM505 SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 www.ti.com Submit Documentation Feedback Specifications Copyright © 2016–2018, Texas Instruments Incorporated Table 5-12. Dual Voltage LVCMOS DC Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER DESCRIPTION MIN NOM MAX UNIT IIN with pulldown enabled Input current at each I/O pin with weak pulldown enabled measured when PAD = VDDS 10 100 290 µA IIN with pullup enabled Input current at each I/O pin with weak pullup enabled measured when PAD = 0 40 100 200 µA CPAD Pad capacitance (including package capacitance) 4 pF ZO Output impedance (drive strength) 40 Ω (1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [10] column. Table 5-13. Analog-to-Digital ADC Subsystem Electrical Specifications over operating free-air temperature range (unless otherwise noted) PARAMETER CONDITIONS MIN NOM MAX UNIT Analog Input Full-scale Input Range adc_vrefp V Vref Should be less than or equal to vdds_18v. 1.62 vdds_18v V Differential Non-Linearity (DNL) -1 1 LSB Integral Non-Linearity (INL) adc_vrefp = vdds_18v ±2 LSB Gain Error adc_vrefp = vdds_18v ±4 LSB Offset Error adc_vrefp = vdds_18v ±3 LSB Input Sampling Capacitance 3.2 5 pF Input Frequency adc_in[7:0] 0 30 kHz Signal-to-Noise Ratio (SNR) Input Signal: 30 kHz sine wave at -0.5 dB Full Scale 50 dB Total Harmonic Distortion (THD) 1.8 Vpp, 30 kHz sine wave 60 dB Spurious Free Dynamic Range 1.8 Vpp, 30 kHz sine wave 60 dB Signal-to-Noise Plus Distortion 1.8 Vpp, 30 kHz sine wave 50 dB adc_vrefp Input Impedance 20 Ω Sampling Dynamics Time from Start to Start 17 Clock Cycles Conversion Time + Error Correction 10 + 1 Clock Cycles Acquisition time 4 Clock Cycles Throughput Rate CLK = 20 MHz (Pin : clk) 1 MSPS Channel to Channel Isolation 90 dB ADC Clock Frequency See Table 5-1 MHz (1) Connect adc_vrefp to vdda_adc when not using a positive external reference voltage. (2) This parameter is valid when the respective AIN terminal is configured to operate as a general-purpose ADC input. (3) The maximum sample rate assumes a conversion time of 13 ADC clock cycles with the acquisition time configured for the minimum of 2 ADC clock cycles, where it takes a total of 15 ADC clock cycles to sample the analog input and convert it to a positive binary weighted digital value. |
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