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RF6001
Rev A3 DS050929
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Part of the POLARIS™ TOTAL RADIO™ Solution
GMSK to GMSK Transitions
GMSK to GMSK EALGN=1 “Normal” FIFO Mode
This is the transition mode between two GMSK bursts in “normal” mode with EALGN set to one. Any “garbage” bits are blanked
during the FIFO loading process and have no effect during the transmit time.
The rules for MD_DLY2 with UAM=0 are as follows:
1. MD_DLY2 begins counting at the end of the current symbol after TX_ST falls on the first burst.
2. While MD_DLY2 is active, data is held in the FIFO and the serial interface stops. When MD_DLY2 expires the next bit is
released from the FIFO and the effective FIFO output clock has a rising edge. In serial mode MCK has a rising edge on the
last G_CNT after MD_DLY2 expires.
3. During the time MD_DLY2 is active the data at the output of the FIFO or serial input is multiplexed to the SDI bit called
G_DEF.
4. If MD_DLY2 is set to zero then MD_DLY2 is disabled.
5. When MD_DLY2 expires then G_CNT begins. (serial only)
6. On the last count of G_CNT, MS pulses. (serial only)
7. If MD_DLY2 is set to zero then G_CNT is ignored and MS will NOT pulse until the next normally occurring 16MCK boundary.
(serial only)
If UAM=1 then the rules change as follows:
1. MD_DLY2 begins counting after TX_ST rises on the next burst.
In this example, the rising edge of TX_ST is aligned to be 8qst before the center of the first tail symbol. The modulator uses
data loaded from the FIFO. MD_DLY2 is set to one to cause a 1qst shift in the transition width and thus exactly meet the ETSI
8.25 symbol guard time.
Once MD_DLY2 expires, the G_DLY is set to 6qst. During the 6qst of G_DLY the data at the modulator input is replaced by
G_DEF. The output of the modulator is held at the guard value. At the end of G_DLY, the tail bit data present at the beginning of
G_DLY is fed to the modulator.
The quarter-symbol shift will cause a phase transition to occur at the start of G_DLY. This transition will occur during the ramp
down region and could be a problem. If the previous 4 symbol times are all 1, as shown in the diagram above, then the modu-
lation is “pinned” to maximum deviation and there will be no glitch when the clocks reset. Also note that this transition does
not exist for EALGN=0 and G_DLY=0.
0
G_DLY
0
0
1
1
1
1
1
1
1
1
0
01
11
1
1
1
1000
1
1
1
12 qst
37qst
G_DLY
Center of
last tail bit
Desired center
of first tail bit
8qst
MD_DLY2=1
Clocks Reset
Effective FIFO
Output Clock
TXST
DAC1
Data at
Mod Output
tail
tail
tail
data
data
tail
tail
tail
guard
G_DEF
guard
guard
guard
guard
guard
Data at
Mod Input
guard
guard
tail
data
data
guard
tail
guard
G_DEF
tail
tail
guard
guard
guard
Data at
FIFO Output
guard
guard
tail
data
data
guard
tail
guard guard
tail
tail
guard
guard
guard
G_DEF
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