MM32F103VCT datasheet(12/89 Pages) MINDMOTION

12 / 89 page

DS_MM32F103xx_o_Ver1.13

Specification

generating the software.

2.2.6

Nested vectored interrupt controller (NVIC)

The device embeds a nested vectored interrupt controller and is able to handle up to 68

maskable interrupt channels (not including the 16 interrupt lines of

Cortex™-M3) with 16 priority levels.

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal inter-

rupt latency.

2.2.7

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of many edge detector lines are used to

generate interrupt/event requests for waking up the system. Each line can be indepen-

dently configured to select the trigger event (rising edge, falling edge, both) and can be

masked independently. A pending register maintains the status of the interrupt requests.

The EXTI can detect an external line with a pulse width shorter than the internal APB2

clock period. All GPIOs can be connected to the 16 external interrupt lines.

2.2.8

Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three

boot options：

• Boot from User Flash memory

• Boot from System Memory

• Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory

by using UART1.

2.2.9

Power supply schemes

• VDD = 2.0V

∼ 5.5V: external power supply for I/Os and the internal regulator. Provided

externally through VDD pins.

• VDDA = 2.0V

∼ 5.5V：external analog power supply for ADC, reset blocks, oscillators

and PLL. VDDA and VSSA 可 can be connected to VDD and VSS separately, Can also be

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