OP467_07 datasheet(5/20 Pages) AD

5 / 20 page

OP467

Rev. F | Page 5 of 20

WAFER TEST LIMITS1

@ VS = ±15.0 V, TA = 25°C, unless otherwise noted.

Table 3.

Parameter

Symbol

Conditions

Limit

Unit

Offset Voltage

VOS

±0.5

mV max

Input Bias Current

VCM = 0 V

600

nA max

Input Offset Current

IOS

VCM = 0 V

100

nA max

Input Voltage Range2

±12

V min/max

Common-Mode Rejection Ratio

CMRR

VCM = ±12 V

dB min

Power Supply Rejection Ratio

PSRR

V = ±4.5 V to ±18 V

dB min

Large Signal Voltage Gain

AVO

RL = 2 kΩ

dB min

Output Voltage Range

RL = 2 kΩ

±13.0

V min

Supply Current

ISY

VO = 0 V, RL = ∞

mA max

1 Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard

product dice. Consult sales to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

2 Guaranteed by CMR test.

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