CY28316

Rev 1.0, November 20, 2006

Page 10 of 17

Bit 5

–

Reserved

0

Reserved.

Bit 4

–

Reserved

0

Reserved.

Bit 3

–

Reserved

0

Reserved.

Bit 2

–

Reserved

0

Reserved.

Bit 1

-

Reserved

0

Reserved.

Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes

Input Conditions

Output Frequency

PLL Gear

Constant (G)

FS4

FS3

FS2

FS1

FS0

CPU

PCI

SEL4

SEL3

SEL2

SEL1

SEL0

0

0

0

0

0

200.0

33.3

48.000741

0

0

0

0

1

190.0

38.0

48.000741

0

0

0

1

0

180.0

36.0

48.000741

0

0

0

1

1

170.0

34.0

48.000741

0

0

1

0

0

166.0

33.2

48.000741

0

0

1

0

1

160.0

32.0

48.000741

0

0

1

1

0

150.0

37.5

48.000741

0

0

1

1

1

145.0

36.3

48.000741

0

1

0

0

0

140.0

35.0

48.000741

0

1

0

0

1

136.0

34.0

48.000741

0

1

0

1

0

130.0

32.5

48.000741

0

1

0

1

1

124.0

31.0

48.000741

0

1

1

0

0

67.2

33.6

48.000741

0

1

1

0

1

100.8

33.6

48.000741

0

1

1

1

0

118.0

39.3

48.000741

0

1

1

1

1

134.4

33.6

48.000741

1

0

0

0

0

67.0

33.5

48.000741

1

0

0

0

1

100.5

33.5

48.000741

1

0

0

1

0

115.0

38.3

48.000741

1

0

0

1

1

134.0

33.5

48.000741

1

0

1

0

0

66.8

33.4

48.000741

1

0

1

0

1

100.2

33.4

48.000741

1

0

1

1

0

110.0

36.7

48.000741

1

0

1

1

1

133.6

33.4

48.000741

1

1

0

0

0

105.0

35.0

48.000741

1

1

0

0

1

90.0

30.0

48.000741

1

1

0

1

0

85.0

28.3

48.000741

1

1

0

1

1

78.0

39.0

48.000741

1

1

1

0

0

66.6

33.3

48.000741

1

1

1

0

1

100.0

33.3

48.000741

1

1

1

1

0

75.0

37.5

48.000741

1

1

1

1

1

133.3

33.3

48.000741

Byte 17: Reserved Register (continued)

Bit

Pin#

Name

Default

Description