CY28316

Rev 1.0, November 20, 2006

Page 5 of 17

CY28316 Serial Configuration Map

1. The serial bits will be read by the clock driver in the following

order:

Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0

2. All unused register bits (reserved and N/A) should be

written to a “0” level.

3. All register bits labeled “Write with 1" must be written to “1”

during initialization.

Byte 0: Control Register 0

Bit

Pin#

Name

Default

Description

Bit 7

–

Spread Select1

0

See definition in Bit[0].

Bit 6

–

SEL2

0

See

Table 5.

Bit 5

–

SEL1

0

See

Table 5.

Bit 4

–

SEL0

0

See

Table 5.

Bit 3

–

FS_Override

0

0 = Select operating frequency by FS[4:0] input pins.

1 = Select operating frequency by SEL[4:0] settings.

Bit 2

–

SEL4

0

See

Table 5.

Bit 1

–

SEL3

0

See

Table 5.

Bit 0

–

Spread Select0

0

‘00’ = OFF.

‘01’ = – 0.5%.

‘10’ = ± 0.5%.

‘11’ = ± 0.25%.

Byte 1: Control Register 1

Bit

Pin#

Name

Default

Description

Bit 7

6

Latched FS4 input

X

Latched FS[4:0] inputs. These bits are read-only.

Bit 6

7

Latched FS3 input

X

Bit 5

46

Latched FS2 input

X

Bit 4

25

Latched FS1 input

X

Bit 3

26

Latched FS0 input

X

Bit 2

44

CPU0

1

(Active/Inactive).

Bit 1

43

CPU1

1

(Active/Inactive).

Bit 0

–

Vendor Test Mode

1

Write with ‘1.’

Byte 2: Control Register 2

Bit

Pin#

Name

Default

Description

Bit 7

40

SDRAM12

1

(Active/Inactive).

Bit 6

6

PCI0

1

(Active/Inactive).

Bit 5

13

PCI6

1

(Active/Inactive).

Bit 4

12

PCI5

1

(Active/Inactive).

Bit 3

11

PCI4

1

(Active/Inactive).

Bit 2

10

PCI3

1

(Active/Inactive).

Bit 1

9

PCI2

1

(Active/Inactive).

Bit 0

7

PCI1

1

(Active/Inactive).