FUNCTIONAL DESCRIPTION (Refer to the

Block Diagram)

The commutation sequence is provided by the

user via six inputs. INUA,INUB,INUC turn on the

three upper DMOS drivers when held at logic

LOW, and inputs INLA,INLB,INLC turn on the

three lower DMOS drivers when held at logic

HIGH.

The BRK and BRK DLY inputs offer flexibility to

the system designer in the implementation of the

braking function. The BRK logic input, when

pulled low will turn-off all upper and lower Dmos

drivers. The low transition at BRK will produce a

delayed negative transition at the BRK DLY input,

configurable by connection of a capacitor Cd and

a resistor Rd from the BRK DLY pin to ground.

The negative transition at BRK DLY will initiate

the braking of the motor by turning on all lower

Dmos, while keeping all upper DMOS turned-off.

This feature provides a time interval where the

motor BEMF can be used to power the head

parking function before the braking procedure is

iniziated. External detection of the supply(VP)

drop-off is necessary to provide the appropriate

logic signal to the BRK input. (see Fig. 1)

The brake function utilizes the energy stored in

the central charge pump capacitor (Cp) to turn-on

or turn-off the DMOS drivers.

This allows for

completion of the braking procedure after the VP

supply has powered down.

The L6232E is capable of driving the motor in

either pulse width modulation (PWM) or linear

(LIN) mode. The driving mode is determined by

the smaller of two analog voltages inputs, LIN

Vref and PWM Vref. The motor current is control-

led by LIN Vref and PWM Vref and the current

sense resistor Rs connected to the SENSE out-

put. The SENSE output provides for connection of

a resistor in series with the source of all lower

DMOS drivers. The voltage at this pin provides

the error signal wich is utilized internally to regu-

late the motor current Im. The current in both

PWM and linear mode is determined by the ex-

pression :

=

in wich Gv is the voltage gain of the sense ampli-

fier. In linear mode, the current is regulated by a

linear control loop wich drives the lower DMOS.

Compensation of the linear control loop is

achieved by connection of a series network

(Rc,Cc) from the transconductance amplifier out-

put (Gm) and ground. Control is passed to each

lower DMOS in succession during the commuta-

tion sequence(MPX).

The rate at which the upper and lower drivers

turns-off during linear mode operation is configur-

able externally by the value of the resistor R used

at the RC pin. This defines a current which is util-

ized internally to limit the voltage slew-rate at the

outputs during transitions. The output slew-rate is

internally adjusted for fast slewing during PWM

operation to reduce losses, and a relatively

slower rate during linear mode operation to mini-

Figure 1: Brake Delay and Braking timing of the L6232E. At the time t1 a VP Powerdown threshold

detector drives low the BRK input; at time t2 the Charge Pump voltage becomes inadequate

to maintain ON the lower DMOS.

L6232E

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