CLC014 datasheet(9/17 Pages) NSC

9 / 17 page

Operation (Continued)

DEVICE TESTING

Performance or compliancy testing of the CLC014 with

Cable Clones is not allowed. Use of these devices is con-

trary to the product’s specifications and test procedures.

Testing for product specifications or performance using cable

clones is invalid since cable clones have a different fre-

quency response than the actual cable. Testing with full

length cable samples is recommended.

Input Interfacing

The CLC014 accepts either differential or single-ended input

voltage specified in Static Performance. The following sec-

tions show several suggestions for interfaces for the inputs

and outputs of the CLC014.

SINGLE-ENDED INPUT INTERFACE: 75

Ω Coaxial Cable

The input is connected single-ended to either DI or DI as

shown in Figure 3. Balancing unused inputs helps to lessen

the effects of noise. Use the equivalent termination of 37.5

Ω

to balance the input impedance seen by each pin. It also

helps to terminate grounds at a common point. Resistors R

and R

y are recommended for optimum performance. The

equalizer inputs are self-biasing. Signals should be AC

coupled to the inputs as shown in Figure 3.

DIFFERENTIAL INPUT INTERFACE: Twisted Pair

A recommended differential input interface is shown in Fig-

ure 4. Proper voltage levels must be furnished to the input

pins and the proper cable terminating impedance must be

provided. For Category 5 UTP this is approximately 100

Ω.

Figure 4 shows a generalized network which may be used to

receive data over a twisted pair. Resistors R

1 and R2 provide

the proper terminating impedance and signal level adjust-

ment. The blocking capacitors provide AC coupling of the

attenuated signal levels. The plots in the Typical Perfor-

mance Characteristics section demonstrate various equal-

ized data rates using Category 5 UTP at 100 meter lengths.

A full schematic of a recommended driver and receiver cir-

cuit for 100

Ω Category 5 UTP is provided in the Typical

Applications section with further explanation.

Output Interfacing

The outputs DO and DO produce ECL logic levels when the

recommended output termination networks are used. The

DO and DO pins are not complementary emitter coupled

logic outputs. Instead, the outputs are taken off of the col-

lectors of the transistors. Therefore, care must be taken to

meet the interface threshold levels required by ECL families.

Recommended interfaces for standard ECL families are

shown in the following circuits.

DIFFERENTIAL LOAD-TERMINATED OUTPUT

INTERFACE

Figure 5 shows a recommended circuit for implementing a

differential output that is terminated at the load. A diode or

Ω resistor provides a voltage drop from the positive supply

(+5V for PECL or Ground for ECL operation) to establish

proper ECL levels. The resistors terminate the cable to the

characteristic impedance. The output voltage swing is deter-

mined by the CLC014 output current (10 mA) times the

termination resistor. For the circuit in Figure 5, the nominal

output voltage swing is 750 mV.

10005621

FIGURE 2. CLC014 Block Diagram

10005622

FIGURE 3. Single-Ended 75

Ω Cable Input Interface

10005624

FIGURE 4. Twisted Pair Input Interface

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