NXP Semiconductors

PCA9537

4-bit I2C-bus and SMBus low power I/O port with interrupt and reset

Legend: * default value.

Bit

Symbol

Access

Value

Description

3

O3

R

1*

2

O2

R

1*

1

O1

R

1*

0

O0

R

1*

reflects outgoing logic levels of pins defined as outputs

by Register 3

Table 6. Register 1 - Output Port register bit description...continued

6.2.4 Register 2 - Polarity Inversion register

This register allows the user to invert the polarity of the Input Port register data. If a bit in

this register is set (written with 1), the corresponding Input Port data is inverted. If a bit in

this register is cleared (written with a 0), the Input Port data polarity is retained.

Legend: * default value.

Bit

Symbol

Access

Value

Description

7

N7

R/W

0*

6

N6

R/W

0*

5

N5

R/W

0*

4

N4

R/W

0*

not used

3

N3

R/W

0*

2

N2

R/W

0*

1

N1

R/W

0*

0

N0

R/W

0*

inverts polarity of Input Port register data

0 = Input Port register data retained (default value)

1 = Input Port register data inverted

Table 7. Register 2 - Polarity Inversion register bit description

6.2.5 Register 3 - Configuration register

This register configures the directions of the I/O pins. If a bit in this register is set, the

corresponding port pin is enabled as an input with high-impedance output driver. If a bit in

this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/

Os are configured as inputs.

Legend: * default value.

Bit

Symbol

Access

Value

Description

7

C7

R/W

1*

6

C6

R/W

1*

5

C5

R/W

1*

4

C4

R/W

1*

not used

3

C3

R/W

1*

2

C2

R/W

1*

1

C1

R/W

1*

0

C0

R/W

1*

configures the directions of the I/O pins

0 = corresponding port pin enabled as an output

1 = corresponding port pin configured as an

input (default value)

Table 8. Register 3 - Configuration register bit description

PCA9537

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© NXP B.V. 2021. All rights reserved.

Product data sheet

Rev. 7 — 8 September 2021

COMPANY PUBLIC

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