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MPF0900AMBA2ES Datasheet(PDF) 182 Page - NXP Semiconductors |
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MPF0900AMBA2ES Datasheet(HTML) 182 Page - NXP Semiconductors |
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182 / 205 page ![]() NXP Semiconductors PF09 Nine-channel power management IC with advanced system safety monitoring 15.3 OTP registers Key Description OTP only OTP-only bits are used to set a hardware and software configuration that is not intended to change during the normal system operation. OTP functional OTP functional values are used to set the default configuration of the I2C functional registers at power up. The system can then modify the functional configuration during system operation as required by the application. Not all OTP functional bits have a one-to-one match in the functional registers, however one or more functional bits may set their default value(s) based on the selection of these bits as described in this document. Table 231. OTP register color code ADDR REGISTER DEFAULT BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 MSB — — — OTP_I2C_ SECURE_EN OTP_I2C_ CRC_EN OTP_I2C_ADD[2:0] 0x60 OTP_I2C_CFG 0000_0000 — — — RW RW RW RW RW MSB OTP_LBIST_ BYPASS OTP_EWARN_TIME[1:0] OTP_ PWRUP_CHK OTP_ STBY_REQ OTP_LP_STBY OTP_ ERRMON_POL OTP_ STBY_POL 0x61 OTP_SYS_ CFG1 0000_0100 RW RW RW RW RW RW RW RW MSB OTP_VIN_SEL OTP_SW1 LS_EN OTP_ XFAILB_EN OTP_XFAILB_ VAON OTP_VIN_ OV_SDWN OTP_VIN_ OV_EN OTP_VIN_OV_DBNC[1:0] 0x62 OTP_SYS_ CFG2 0000_0000 RW — RW RW RW RW RW RW MSB OTP_ GPO4_STBY OTP_ GPO3_STBY OTP_ GPO2_STBY OTP_ GPO1_STBY OTP_SW4CONFIG[1:0] OTP_SW2CONFIG[1:0] 0x63 OTP_SYS_ CFG3 0000_0000 RW RW RW RW RW RW RW RW MSB OTP_GPIO4_MODE[1:0] OTP_GPIO3_MODE[1:0] OTP_GPIO2_MODE[1:0] OTP_GPIO1_MODE[1:0] 0x64 OTP_SYS_ CFG4 0000_0000 RW RW RW RW — — — RW MSB — OTP_RETRY_MSK[3:0] OTP_RETRY_ MODE OTP_ RETRY_DFS OTP_ PWRON_DFS 0x65 OTP_DFS_CFG 0000_0001 — RW RW RW RW RW RW RW MSB — OTP_VDIGOV_RSTB[1:0] OTP_BGM_RSTB[1:0] OTP_SHS_RSTB[2:0] 0x66 OTP_DMS_ CFG1 0000_0000 — RW RW RW RW RW RW RW MSB — OTP_VDIGOV_CUTOFF[1:0] OTP_BGM_CUTOFF[1:0] OTP_SHS_CUTOFF[2:0] 0x67 OTP_DMS_ CFG2 0000_0000 — RW RW RW RW RW RW RW MSB — OTP_FSYNC_ MODE OTP_FSS_ MODE OTP_FSS_EN OTP_CLK_FREQ[3:0] 0x68 OTP_ FREQ_CFG 0000_0100 — RW RW RW RW RW RW RW MSB OTP_WD_DURATION[3:0] — OTP_WD_WINDOW[1:0] OTP_WD_EN 0x69 OTP_WD_CFG1 0000_0000 RW RW RW RW — RW RW RW MSB — OTP_WD_NOK_MAX[2:0] — OTP_WD_OK_FCD[2:0] 0x6A OTP_WD_CFG2 0000_0000 — RW RW RW — RW RW RW MSB OTP_TIMER_FAULT[3:0] OTP_FAULT_MAX_CNT[3:0] 0x6B OTP_ FAULT_CNT 0000_0000 RW RW RW RW RW RW RW RW MSB OTP_MAX_FS_CNT[3:0] OTP_RESET_MAX[3:0] 0x6C OTP_FAULT_ CNT2 0000_0000 RW RW RW RW RW RW RW RW MSB — — OTP_RSTB_SOFTRST[1:0] OTP_RSTB_MODE[1:0] OTP_RSTB_TSHORT[1:0] 0x6D OTP_ RSTB_CFG 0000_0000 — — — RW RW RW RW RW MSB OTP_FS0 B_DCRC OTP_FS0 B_DFS OTP_FS0 B_VIN_OV OTP_FS0 B_XFAIL OTP_FS0 B_WD OTP_FS0 B_XRESET OTP_FS0 B_SFAULT OTP_FS0 B_HFAULT 0x6E OTP_FS0 B_CFG 0000_0000 RW RW RW RW RW RW RW RW MSB OTP_FCCU1_MODE[1:0] OTP_FCCU0_MODE[1:0] OTP_ FCCU1_POL OTP_ FCCU0_POL OTP_FCCU_DBNC[1:0] 0x6F OTP_ FCCU_CFG 0000_0000 RW RW RW RW RW RW RW RW Table 232. OTP Register Map PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback 182 / 205 |
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