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MPF0900AMBA2ES Datasheet(PDF) 85 Page - NXP Semiconductors

Part # MPF0900AMBA2ES
Description  Nine-channel power management IC with advanced system safety monitoring
PDF  205 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPF0900AMBA2ES Datasheet(HTML) 85 Page - NXP Semiconductors

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NXP Semiconductors
PF09
Nine-channel power management IC with advanced system safety monitoring
The PF09 provides various mechanisms on the I2C communication protocol to ensure proper communication
and avoid system failures that could be caused by incorrect data.
12.8.14.1 I2C CRC verification
The I2C CRC mechanism is provide to verify the integrity of each I2C transaction. The CRC is enabled via the
OTP_I2C_CRC_EN bit.
OTP_I2C_CRC_EN
I2C CRC
0
Disabled
1
Enabled
Table 102. Enabling the I2C CRC mechanism
The CRC calculation is based on the standard CRC-8-SAE as defined in the SAE-J1850 specificationn with the
following characteristics.
Polynomial = 0x1D
Initial value = 0xFF
The CRC byte is calculated by shifting 24-bit data through the CRC polynomial. The 24-bit package is built as
follows:
DEVICE_ADDR[b8] + REGISTER_ADDR [b8] +DATA[b8]
The DEVICE_ADDR is calculated as the seven-bit secondary address shifted left one space plus the
corresponding read/write bit. (7Bit Address [b7] << 1 ) + R/W = DEVICE_ADDR[b8]
aaa-056069
DEVICE_ADDR
[6:0]
R/W
[1]
MSB
data
7
6
5
4
3
+
+
REGISTER_ADDR
[7:0]
Polynominal = 0x1D
x8 + x4 + x3 + x2 + 1
Seed = 1111 1111
DATA
[7:0]
+
2
1
0
Figure 24. I2C CRC Polynomial
During an I2C write command, the MCU must calculate the CRC byte and send it after the data byte in the I2C
package, to make a total of 32 bits per transaction.
After each I2C write transaction, the device calculates the corresponding CRC byte internally and compares it to
the CRC sent by the MCU, to ensure the configuration command has not been corrupted.
When a CRC fault is detected, the device ignores the current configuration command and sets the I2C_CRC_I.
the I2C CRC interrupt will assert the INTB pin if the interrupt is not masked.
12.8.14.2 I2C secure write
A secure write protocol is implemented for specific registers critical to the functional safety of the device. The
secure write functionality is enabled by the I2C_SECURE_EN bit, and the default value is set at power up via
the OTP_I2C_SECURE_EN bit.
PF09
All information provided in this document is subject to legal disclaimers.
© 2026 NXP B.V. All rights reserved.
Product data sheet
Rev. 1.3 — 16 December 2025
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