CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *B
Page 4 of 19
Maximum Ratings[12]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65
°C to +150°C
Ambient Temperature with
Power Applied.............................................–55
°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State............................–0.5V to VCC+0.5V
DC Input Voltage......................................–0.5V to VCC+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >1100V
Latch-Up Current...................................................... >200mA
Note:
12. The voltage on any input or I/O pin can not exceed the power pin during power-up.
Pin Definitions
Left Port
Right Port
Description
A0L–A15L
A0R–A15R
Address Inputs (A0–A14 for 32K, A0–A13 for 16K devices).
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads the
burst counter with the address present on the address pins.
CE0L,CE1L
CE0R,CE1R
Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted
to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
CLKL
CLKR
Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its
respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O17L
I/O0R–I/O17R Data Bus Input/Output (I/O0–I/O15 for x16 devices).
LBL
LBR
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lower byte. (I/O0–I/O8 for x18, I/O0–I/O7 for x16) of the memory array. For read operations both
the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.
UBL
UBR
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L–I/O15/17L).
OEL
OER
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/WL
R/WR
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
FT/PIPEL
FT/PIPER
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
GND
Ground Input.
NC
No Connect.
VCC
Power Input.
Operating Range
Range
Ambient
Temperature
VCC
Commercial
0
°C to +70°C
3.3V
± 300 mV
Industrial
–40
°C to +85°C
3.3V
± 300 mV
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