PRELIMINARY
CY28341-3
Document #: 38-07580 Rev. **
Page 10 of 19
P4 Processor SELP4_K7# = 1
Power-down Assertion (P4 Mode)
When PD# is sampled low by two consecutive rising edges of
CPU# clock then all clock outputs except CPU clocks must be
held low on their next high to low transition. CPU clocks must
be held with the CPU clock pin driven high with a value of
2 x Iref, and CPU# undriven. Note that Figure 1 shows
CPU = 133 MHz. This diagram and description are applicable
for all valid CPU frequencies 66, 100, 133, 200 MHz. Due to
the state of internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock
cycle to complete.
Power-down Deassertion (P4 Mode)
The power-up latency needs to be less than 3 mS.
AMD K7 processor SELP4_K7# = 0
Power-down Assertion (K7 Mode)
When the PD# signal is asserted low, all clocks are disabled
to a low level in an orderly fashion prior to removing power
from the part. When PD# is asserted (forced) low, the device
transitions to a shutdown (power down) mode and all power
supplies may then be removed. When PD# is sampled low by
two consecutive rising edges of CPU clock, then all affected
clocks are stopped in a low state as soon as possible. When
in power down (and before power is removed), all outputs are
synchronously stopped in a low state (see Figure 3 below), all
PLL's are shut off, and the crystal oscillator is disabled. When
the device is shutdown, the I2C function is also disabled.
PC I 33M H z
PD #
CPUT 133M H z
CPUC 133M H z
R E F 14.318M H z
USB 48M H z
DD RT 133M H z
D D R C 133M H z
AG P 66M H z
Figure 2. Power-down Assertion Timing Waveform (in P4 Mode)
PC I 33M H z
PD #
CP UT 133M Hz
CP UC 133M Hz
AG P 66M H z
R E F 14.318M H z
U SB 48M H z
<1.5 m sec
DDRT 133M Hz
DDRC 133M Hz
Figure 3. Power-down Deassertion Timing Waveform (in P4 mode)
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
