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Ten Output Zero Delay Buffer
W232
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07167 Rev. *B
Revised December 15, 2002
Features
• Well-suited to both 100- and 133-MHz designs
• Ten/eleven LVCMOS/LVTTL outputs
• 3.3V power supply
• Available in 24-pin TSSOP package
Key Specifications
Operating Voltage: .............................................. 3.3V ± 10%
Operating Range: ........................25 MHz < fOUT < 140 MHz
Cycle-to-Cycle Jitter: ...............................................< 150 ps
Output to Output Skew: ...........................................< 100 ps
Phase Error Jitter: ....................................................< 125 ps
Static Phase Error: ...................................................< 150 ps
Block Diagram
Pin Configurations
CLK
AVDD
VDD
Q8
Q7
GND
GND
Q6
Q5
VDD
OE5:8
FBIN
24
23
22
21
20
19
18
17
16
15
14
13
AGND
VDD
Q0
Q1
Q2
GND
GND
Q3
Q4
VDD
OE0:4
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
Q0
PLL
Q1
Q2
Q3
Q5
Q6
OE0:4
Q7
Q8
FBOUT
Q4
Q9
OE
OE5:8
Configuration of these blocks dependent upon specific option being used.
FBIN
CLK
CLK
AVDD
VDD
Q9
Q8
GND
GND
Q7
Q6
Q5
VDD
FBIN
24
23
22
21
20
19
18
17
16
15
14
13
AGND
VDD
Q0
Q1
Q2
GND
GND
Q3
Q4
VDD
OE
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
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