TAS5706PAPR datasheet(37/62 Pages) TI

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APPLICATION INFORMATION

Recovery From Error

Interchannel Delay (ICD) Settings

Calculation of Output Signal Level of TAS5706 Feedback Power Stage

TAS5706

SLOS550A – DECEMBER 2007 – REVISED DECEMBER 2007

Protection Mechanisms in the TAS5706

• SCP (short-circuit protection, OCP) protects against shorts across the load, to GND, and to PVCC.

• OTP turns off the device if T

die (typical) > 150°C.

• UVP turns off the device if PVCC (typical) < 8.4 V

• OVP turns off the device if PVCC (typical) > 27.5 V

A short-circuit condition can be detected also by an external controller. The SCP error from the external power

stage is also fed into TAS5706. The VALID pin goes low in the event of a short circuit. The VALID pin can be

monitored by an external

µC. The TAS5706 initiates a back-end error sequence by itself to recover from the

error, which involves settling VALID low for a programmable amount of time and then retrying to check whether

the SCP condition still exists.

• OTP turns on the device back when T

die(typical) < 135°C.

• UVP turns on the device if PVCC (typical) is > 8.5 V.

• OVP turns on the device if PVCC (typical) is < 27.2 V.

Recommended ICD Settings

Mode

Description

ICD1

ICD2

ICD3

ICD4

ICD5

ICD6

2.0 ch BD BTL

2 BTL channels, internal

A(L+) = 19

C(R+) = 13

B(L–) = 7

D(R–) = 25

SM(S–) = –12 SP(S+) = –28

power stage only, BD

(0x4C)

(0x34)

(0x1C)

(0x64)

(0xD0)

(0x90)

mode

2.1 ch AD BTL

2 internal BTL channels,

A(L+) = 23

C(R+) = 9

B(L–) = 21

D(R–) = 11

SM(S–) = –23 SP(S+) = –21

1 external BTL channel

(0x5C)

(0x24)

(0x54)

(0x2C)

(0xA4)

(0xAC)

using PBTL TAS5601,

AD mode

2.1 ch AD SE

2 internal SE channels (2

A(L+) = 15

B(R–) = –15

B(0) = 0

D(0) = 0

SM(S–) = –30 SP(S+) = –32

unused), 1 external BTL

(0x3C)

(0xC4)

(0x00)

(0x88)

(0x80)

channel using PBTL

TAS5601, AD mode

2.1 ch BD BTL

2 internal BTL channels,

A(L+) = 19

C(R+) = 13

B(L–) = 7

D(R–) = 25

SM(S–) = –12 SP(S+) = –28

1 external BTL channel

(0x4C)

(0x34)

(0x1C)

(0x64 )

(0xD0)

(0x90)

using PBTL TAS5601,

BD mode

3.0 ch AD 2SE + 2 internal SE channels +

A(L+) = 15

B(R–) = –16

SM(0) = 0

SP(0) = 0

D(S–) = 0

C(S+) = 2

1 BTL

1 internal BTL channel,

(0x3C)

(0xC0)

(0x00)

(0x08)

AD mode

4.0 ch AD SE

4 internal SE channels

A(L1+) = 8

B(R1–) = –24

C(L2+) = –8

D(R2–) = 24

SM(0) = 1

SP(0) = –1

(=0x20)

(0xA0)

(0xE0)

(0x60)

(0x04)

(0xFC)

4.1 ch AD SE

4 internal SE channels +

A(L1+) = 8

B(R1–) = –24

C(L2+) = –8

D(R2–)= 24

SM(S–) = 1

SP(S+) = –1

1 external BTL channel,

(0x20)

(0xA0)

(xE0)

(0x60)

(0x04)

(0xFC)

using PBTL TAS5601,

AD mode.

(Gain Is independent of PVCC)

The gain of the TAS5706 is the total digital gain of the controller multiplied by the gain of the power stage.

For a half-bridge channel of the TAS5706 power stage, the gain is simply:

Power stage gain = 13

× V

RMS / Modulation Level

Modulation level = fraction of full-scale modulation of the PWM signal at the input of the power stage.

VRMS = Audio voltage level at the output of the power stage = 13 × Modulation Level

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