M24256-A datasheet(4/20 Pages) STMICROELECTRONICS

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M24256-A

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unconnected, the WC input is internally read as

VIL, and write operations are allowed.

When WC=1, Device Select and Address bytes

are acknowledged, Data bytes are not acknowl-

edged.

Please see the Application Note

AN404 for a more

detailed description of the Write Control feature.

DEVICE OPERATION

The memory device supports the I2C protocol.

This is summarized in Figure 4, and is compared

with other serial bus protocols in Application Note

AN1001. Any device that sends data on to the bus

is defined to be a transmitter, and any device that

reads the data to be a receiver. The device that

controls the data transfer is known as the master,

and the other as the slave. A data transfer can only

be initiated by the master, which will also provide

the serial clock for synchronization. The memory

device is always a slave device in all communica-

tion.

Start Condition

START is identified by a high to low transition of

the SDA line while the clock, SCL, is stable in the

high state. A START condition must precede any

data transfer command. The memory device con-

tinuously monitors (except during a programming

cycle) the SDA and SCL lines for a START condi-

tion, and will not respond unless one is given.

Stop Condition

STOP is identified by a low to high transition of the

SDA line while the clock SCL is stable in the high

state. A STOP condition terminates communica-

tion between the memory device and the bus mas-

ter. A STOP condition at the end of a Read

command, after (and only after) a NoAck, forces

the memory device into its standby state. A STOP

condition at the end of a Write command triggers

the internal EEPROM write cycle.

Figure 4. I2C Bus Protocol

SCL

SDA

SCL

SDA

START

Condition

SDA

Input

SDA

Change

AI00792B

STOP

Condition

MSB

ACK

START

Condition

SCL

MSB

ACK

STOP

Condition

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