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TMS320DM641 Datasheet(PDF) 101 Page - Texas Instruments |
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TMS320DM641 Datasheet(HTML) 101 Page - Texas Instruments |
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101 / 179 page  Clock PLL 101 June 2003 − Revised October 2005 SPRS222E Table 4−12. TMS320DM641/DM640 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time†‡ GDK and ZDK PACKAGES − 23 x 23 mm BGA, GNZ and ZNZ PACKAGES − 27 x 27 mm BGA CLKMODE1 CLKMODE0 CLKMODE (PLL MULTIPLY FACTORS) CLKIN RANGE (MHz) CPU CLOCK FREQUENCY RANGE (MHz) CLKOUT4 RANGE (MHz) CLKOUT6 RANGE (MHz) TYPICAL LOCK TIME (µs)§ 0 0 Bypass (x1) 30−75 30−75 7.5−18.8 5−12.5 N/A 0 1 x6 30−75 180−450 45−112.5 30−75 75 1 0 x12 30−50 360−600 90−150 60−100 75 1 1 Reserved − − − − − † These clock frequency range values are applicable to a DM641−600 speed device. For −400, −500 device speed values, see the CLKIN timing requirements table for the specific device speed. ‡ Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the DM641/DM640 device to one of the valid PLL multiply clock modes (x6 or x12). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass). § Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs. 4.7.2 Clock PLL Electrical Data/Timing (Input and Output Clocks) Table 4−13. Timing Requirements for CLKIN for −400 Devices†‡§ (see Figure 4−13) −400 NO. PLL MODE x12 PLL MODE x6 x1 (BYPASS) UNIT NO. MIN MAX MIN MAX MIN MAX UNIT 1 tc(CLKIN) Cycle time, CLKIN 30 33.3 13.3 33.3 13.3 33.3 ns 2 tw(CLKINH) Pulse duration, CLKIN high 0.45C 0.45C 0.45C ns 3 tw(CLKINL) Pulse duration, CLKIN low 0.45C 0.45C 0.45C ns 4 tt(CLKIN) Transition time, CLKIN 5 5 1 ns 5 tJ(CLKIN) Period jitter, CLKIN 0.02C 0.02C 0.02C ns † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. § C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. Table 4−14. Timing Requirements for CLKIN for −500 Devices†‡§ (see Figure 4−13) −500 NO. PLL MODE x12 PLL MODE x6 x1 (BYPASS) UNIT NO. MIN MAX MIN MAX MIN MAX UNIT 1 tc(CLKIN) Cycle time, CLKIN 24 33.3 13.3 33.3 13.3 33.3 ns 2 tw(CLKINH) Pulse duration, CLKIN high 0.45C 0.45C 0.45C ns 3 tw(CLKINL) Pulse duration, CLKIN low 0.45C 0.45C 0.45C ns 4 tt(CLKIN) Transition time, CLKIN 5 5 1 ns 5 tJ(CLKIN) Period jitter, CLKIN 0.02C 0.02C 0.02C ns † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. § C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. |
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