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TMS320DM641 Datasheet(PDF) 104 Page - Texas Instruments

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Part # TMS320DM641
Description  Video/Imaging Fixed-Point Digital Signal Processors
PDF  179 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM641 Datasheet(HTML) 104 Page - Texas Instruments

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Clock PLL
104
June 2003 − Revised October 2005
SPRS222E
Table 4−19. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the
EMIFA Module§#|| (see Figure 4−17)
NO.
PARAMETER
−400
−500
−600
UNIT
MIN
MAX
1
tw(EKO1H)
Pulse duration, AECLKOUT1 high
EH − 0.7
EH + 0.7
ns
2
tw(EKO1L)
Pulse duration, AECLKOUT1 low
EL − 0.7
EL + 0.7
ns
3
tt(EKO1)
Transition time, AECLKOUT1
1
ns
4
td(EKIH-EKO1H)
Delay time, AECLKIN high to AECLKOUT1 high
1
8
ns
5
td(EKIL-EKO1L)
Delay time, AECLKIN low to AECLKOUT1 low
1
8
ns
§ E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
# The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
|| EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
kThis cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
4
5
1
2
AECLKIN
AECLKOUT1
3
3
Figure 4−17. AECLKOUT1 Timing for the EMIFA Module
Table 4−20. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the
EMIFA Module†‡ (see Figure 4−18)
NO.
PARAMETER
−400
−500
−600
UNIT
MIN
MAX
1
tw(EKO2H)
Pulse duration, AECLKOUT2 high
0.5NE − 0.7
0.5NE + 0.7
ns
2
tw(EKO2L)
Pulse duration, AECLKOUT2 low
0.5NE − 0.7
0.5NE + 0.7
ns
3
tt(EKO2)
Transition time, AECLKOUT2
1
ns
4
td(EKIH-EKO2H)
Delay time, AECLKIN high to AECLKOUT2 high
1
8
ns
5
td(EKIL-EKO2L)
Delay time, AECLKIN low to AECLKOUT2 low
1
8
ns
† The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡ E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
N = the EMIF input clock divider; N = 1, 2, or 4.
§ This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
4
5
1
2
AECLKIN
AECLKOUT2
3
3
Figure 4−18. AECLKOUT2 Timing for the EMIFA Module



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