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ECLKOUTx

(Output from DSP)

ECLKOUTx

(Input to External Device)

Control Signals(A)

(Output from DSP)

Control Signals

(Input to External Device)

Data Signals(B)

(Output from External Device)

Data Signals(B)

(Input to DSP)

A. Control signals include data for Writes.

B. Data signals are generated during Reads from an external device.

5.2 Recommended Clock and Control Signal Transition Behavior

5.3 Power Supplies

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269C – FEBRUARY 2005 – REVISED JANUARY 2007

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external

device and from the external device to the DSP. This round-trip delay tends to negatively impact the input

setup time margin, but also tends to improve the input hold time margins (see Table 5-1 and Figure 5-6).

Figure 5-6 represents a general transfer between the DSP and an external device. The figure also

represents board route delays and how they are perceived by the DSP and the external device.

Table 5-1. Board-Level Timing Example

(see Figure 5-6)

NO.

DESCRIPTION

Clock route delay

Minimum DSP hold time

Minimum DSP setup time

External device hold time requirement

External device setup time requirement

Control signal route delay

External device hold time

External device access time

DSP hold time requirement

DSP setup time requirement

Data route delay

Figure 5-6. Board-Level Input/Output Timings

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner.

For more information regarding TI's power management products and suggested devices to power TI

DSPs, visit www.ti.com/dsppower.

DM643 Peripheral Information and Electrical Specifications

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