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STA027 Datasheet(PDF) 19 Page - STMicroelectronics |
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STA027 Datasheet(HTML) 19 Page - STMicroelectronics |
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19 / 44 page ![]() STA027 5 Register description CD00066274 19/44 Type : RW - DEC Software Reset : 0 Description : This register must contain a PEL value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. Default value at soft reset assume : – external crystal provide a CRYCK running at 14.31818 MHz 5.3.2 PLL_SYSTEM_PEH_50 : Address : 0xE7 (231) Type : RW - DEC Software Reset : 0 Description : This register must contain a PEH value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. Default value at soft reset assume : – external crystal provide a CRYCK running at 14.31818 MHz 5.3.3 PLL_SYSTEM_NDIV_50 : Address : 0xE8 (232) Type : RW - DEC Software Reset : 0 Description : This register must contain a NDIV value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. Default value at soft reset assume : – external crystal provide a CRYCK running at 14.31818 MHz b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 |
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