HT82K68A datasheet(13/30 Pages) HOLTEK

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HT82K68A

Rev. 1.10

November 20, 2001

Input/output ports

There are 32 bidirectional input/output lines in the

HT82K68A, labeled from PA to PE, which are mapped to

the data memory of [12H], [14H], [16H], [18H] and [1AH]

respectively. All these I/O ports can be used for input and

output operations. For input operation, these ports are

non-latching, that is, the inputs must be ready at the T2

rising edge of instruction MOV A,[m] (m=12H, 14H, 16H,

18H or 1AH). For output operation, all data is latched and

remains unchanged until the output latch is rewritten.

Each I/O line has its own control register (PAC, PBC, PCC,

PDC, PEC) to control the input/output configuration. With

this control register, CMOS output or Schmitt trigger input

with or without pull-high resistor (mask option) structures

can be reconfigured dynamically (i.e., on-the-fly) under

software control. To function as an input, the correspond-

ing latch of the control register must write

²1².The

pull-high resistance will exhibit automatically if the

pull-high option is selected. The input source(s) also de-

pend(s) on the control register. If the control register bit is

²1², input will read the pad state. If the control register bit is

²0², the contents of the latches will move to the internal

bus. The latter is possible in

²read-modify-write² instruc-

tion. For output function, CMOS is the only configuration.

These control registers are mapped to locations 13H, 15H,

17H, 19H and 1BH.

After a chip reset, these input/output lines stay at high

levels or floating (mask option). Each bit of these in-

put/output latches can be set or cleared by the SET [m].i

or CLR [m].i (m=12H, 14H, 16H, 18H or 1AH) instruc-

tion.

Some instructions first input data and then follow the

output operations. For example, the SET [m].i, CLR

[m].i, CPL [m] and CPLA [m] instructions read the entire

port states into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A and port C [0:3] has the capability to

wake-up the device.

PC2 is shared with the external interrupt pin, PE2~PE4

is defined as CMOS output pins only. PE0 can deter-

mine whether the high to low transition, or the low to

high transition of PC2 to activate the external subrou-

tine, when PE0 output high, the low to high transition of

PC2 to trigger the external subroutine, when PE0 output

low, the high to low transition of PC2 to trigger the exter-

nal subroutine.

PE2~PE4 is configured as CMOS output only and is

used to drive the LED. PC0, PC1 is configured as

NMOS open drain output with 4.6k

W pull-high resistor

such that it can easy to use as DATA or CLOCK line of

PS2 keyboard application.

D D

C K

D D

D a t a B u s

r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

r i t e I / O

R e a d I / O

S y s t e m

a k e - u p

( P A

P C 0 ~ P C 3 o n l y )

e a k

P u l l - u p

P A 0 ~ P A 7

P B 0 ~ P B 7

M a s k O p t i o n

P C 0 ~ P C 7

P D 0 ~ P D 7

P E 0 ~ P E 4

Input/output ports

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