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©2018 Integrated Device Technology, Inc.

November 9, 2018

9FGL6241 / 9FGL6251 Datasheet

1 Guaranteed by design and characterization, not 100% tested in production.

2 Internal crystal, external crystal may be tuned to 0ppm.

3 Default SMBus value.

4 When driven by a crystal.

5 When driven by an external oscillator via the XIN/CLKIN pin, XO should be floating.

Power Management

1 Polarity of CC_IR is determined by Byte3[3].

2 CC_IR Mode is determined by the status of the input clock associated with the first ePERstn# to deassert.

3 Rising arrow indicates first ePERst# to deassert. Once an ePERst# has gone high, the other ePERst# is ignored.

1 Polarity of CC_IR is determined by Byte3[3].

2 When set to 1, the device only responds to DIF_INA and ePERst0#. ePERst1# must remain low and never deassert.

Table 14. REF Output

Parameter

Symbol

Conditions

Minimum Typical

Maximum Units Notes

Long Accuracy

ppm

Independent Reference Mode.

-100

0

100

ppm

1,2

Long Accuracy

ppm

Common Clock Mode.

0

ppm

1,2

Clock Period

Tperiod25M 25MHz reference input.

40

ns

2

Tperiod33M 33 1/3MHz reference input.

30

ns

2

Rise/Fall Slew Rate

trf1

Slowest slew rate, 20% to 80% of VDDREF.

0.5

0.89

1.6

V/ns

1

trf2

Slow slew rate, 20% to 80% of VDDREF.

0.8

1.5

2.3

V/ns

1,3

trf3

Fast slew rate, 20% to 80% of VDDREF.

0.8

1.5

2.3

V/ns

1

trf4

Fastest slew rate, 20% to 80% of VDDREF.

1.0

1.7

2.4

V/ns

1

Duty Cycle

dt1X

VT = VDD/2 V.

45

48.2

55

%

1,4

Duty Cycle Distortion

dtcd

VT = VDD/2 V.

-0.75

0.00

0

%

1,5

Jitter, Cycle to Cycle

tjcyc-cyc

VT = VDD/2 V.

52

250

ps

1,4

Table 15. Operating Configuration Table (Byte0, bit 5 = 0)

ePERst0#

DIF_INA

ePERst1#

DIF_INB

DIF0

DIF1

CC_IR1,2

↑

No clock present

0

X

From PLL

From PLL

IR Mode

↑

Clock present

0

X

Input A

Input B

CC Mode

0X

↑

No clock present

From PLL

From PLL

IR Mode

0X

↑

Clock present

Input A

Input B

CC Mode

Table 16. Operating Configuration Table (Byte0, bit 5 = 1)

ePERst0#

DIF_INA

ePERst1#

DIF_INB

DIF0

DIF1

CC_IR1,2

↑

No clock present

X

X

From PLL

From PLL

IR Mode

↑

Clock present

X

X

Input A

Input A

CC Mode