6 Detailed Description

6.1 Overview

The Functional Block Diagram section presents the on-chip block level components of the TMF0020 device. The

device has the following data components: a 20480-bit FRAM data memory, and a 64-bit factor-programmed

ROM, which contains an 8-bit family code, a 48-bit identification number, and an 8-bit CRC value. Power for read

and write operations is derived from the SDQ single-wire serial interface pin. An internal capacitor stores energy

while the signal line is high and releases energy during the low times of the SDQ single-wire serial interface pin

until the pin returns high to replenish the charge on the capacitor.

6.2 Functional Block Diagram

TMF0020

RPUP ~ 500

µC

VPUP

GND

ESD

Internal

Charge

Storage

SDQ

Power

Conditioning

MCLK

DIGITAL

FRAM

20kb

OTP

64bit unique ID

Figure 6-1. Functional Block Diagram

6.3 Feature Description

6.3.1 20480-Bit FRAM

Table 6-1 is a memory map of the 20480-bit FRAM section of the TMF0020 device, configured as 80 pages with

32-bytes each. Eight adjacent pages form one 256-byte block. The FRAM memory is programmed using the

32-byte volatile scratchpad buffer. The process for writing to the FRAM memory includes two steps. Data is first

written to the scratchpad buffer. The data is then verified by reading the scratchpad buffer which confirms proper

receipt of the data. If the buffer content is correct, a copy scratchpad command is issued to copy the scratchpad

buffer to the FRAM memory. This process verifies data integrity when programming the memory. The details for

programming and reading the 20480-bit FRAM portion of the TMF0020 are in the Memory Function Commands

section of this data sheet.

Table 6-1. FRAM Data Memory Map

ADDRESS RANGE

TYPE (1)

DESCRIPTION

PROTECTION CODES (NOTES)

0000h to 00FFh

R/(W)

Data Memory Pages 0 to 7 (Block 0)

(Protection controlled by address 1FA0h)

0100h to 01FFh

R/(W)

Data Memory Pages 8 to 15 (Block 1)

(Protection controlled by address 1FA1h)

0200h to 02FFh

R/(W)

Data Memory Pages 16 to 23 (Block 2)

(Protection controlled by address 1FA2h)

0300h to 03FFh

R/(W)

Data Memory Pages 24 to 31 (Block 3)

(Protection controlled by address 1FA3h)

0400h to 04FFh

R/(W)

Data Memory Pages 32 to 39 (Block 4)

(Protection controlled by address 1FA4h)

0500h to 05FFh

R/(W)

Data Memory Pages 40 to 47 (Block 5)

(Protection controlled by address 1FA5h)

0600h to 06FFh

R/(W)

Data Memory Pages 48 to 55 (Block 6)

(Protection controlled by address 1FA6h)

0700h to 07FFh

R/(W)

Data Memory Pages 56 to 63 (Block 7)

(Protection controlled by address 1FA7h)

0800h to 08FFh

R/(W)

Data Memory Pages 64 to 71 (Block 8)

(Protection controlled by address 1FA8h)

TMF0020

SLVSJQ4 – MAY 2026

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