Datasheet

NJM431S/NJM432S

- 3 -

Ver.1.0

■ TEST CIRCUIT

Fig.1 Test Circuit for VKA=VREF

Fig. 2 Test Circuit for VKA>VREF

Fig.3 Test Circuit for IOFF

VO=VKA=VREF

1

R

I

2

R

1

R

1

V

V

V

REF

REF

KA

O

×

+











 +

=

=

■ POWER DISSIPATION vs. AMBIENT TEMPERATURE

(*2) Mounted on glass epoxy board. (76.2 × 114.3 × 1.6mm: EIA/JEDEC standard size, 2Layers)

(*3) Mounted on glass epoxy board. (76.2 × 114.3 × 1.6mm: EIA/JEDEC standard size, 4Layers)

(For 4Layers: Applying 74.2×74.2mm inner Cu area and a thermal via hole to a board based on JEDEC standard JESD51-5)

(*4) Mounted on glass epoxy board. (76.2 × 114.3 × 1.6mm: EIA/JEDEC standard size, 2Layers)

(*5) Mounted on glass epoxy board. (76.2 × 114.3 × 1.6mm: EIA/JEDEC standard size, 4Layers),

internal Cu area: 74.2 × 74.2mm

0

200

400

600

800

1000

1200

1400

1600

-50

-25

0

25

50

75

100

125

150

Ambient Temperature : Ta [ºC]

NJM431SU / NJM432SU (SOT-89-3)

Power Dissipation

(Topr=-40ºC to +125ºC, Tj=150ºC)

(*3) on 4 Layers Board

(*2) on 2 Layers Board

0

100

200

300

400

500

600

700

800

-50

-25

0

25

50

75

100

125

150

Ambient Temperature : Ta [ºC]

NJM431SF / NJM432SF (SOT-23-5)

Power Dissipation

(Topr=-40ºC to +125ºC, Tj=150ºC)

(*5) on 4 Layers Board

(*4) on 2 Layers Board

INPUT

VKA

IK

VREF

INPUT

VKA

IK

VREF

IREF

R1

R2

INPUT

VKA

IOFF