ISOTMP35RDFPR datasheet(26/44 Pages) TI2

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8.1.5.1 Filtering Techniques

EMI mitigation begins at the schematic level. Low-pass filtering can be applied to the VOUT signal path to

attenuate high-frequency noise before the signal reaches the ADC.

A typical implementation includes a capacitor (CLOAD) placed at the VOUT pin and an RC filter located near the

ADC input. The capacitor at the device output provides local high-frequency filtering and reduces output noise.

Because this capacitor directly loads the output stage, the CLOAD value must be selected in accordance with the

capacitive-load drive capability described in Section 7.3.2.2.

A series resistor (RISO) is used to isolate the sensor output from downstream capacitance and improve stability.

When RISO is greater than or equal to 300Ω, the output maintains a phase margin of at least 45° across the full

capacitive-load range, allowing greater flexibility in downstream filtering.

The RC network at the ADC input attenuates high-frequency noise and isolates the sensor output from ADC

sampling transients. Additional RC filtering stages can be used in applications with long routing distances or

elevated noise levels.

Optional ferrite beads can be inserted in the signal path or supply path to suppress high-frequency interference.

The use of ferrite beads must be evaluated at the system level, as frequency-dependent impedance can

introduce signal distortion if not properly selected.

Figure 8-3 shows an example multi-stage filtering configuration intended for high-EMI environments or systems

with long signal routing distances. In most applications, a single RC stage at the ADC input combined with a

properly selected RISO is sufficient.

Keep space beneath

device free of any planes,

traces, pads and vias

VDD

VOUT

GND

ISOTMP35R

Heat

High Voltage Heat Source

GND

CFLT_2

RFLT_2

RFLT_1

CFLT_1

CLOAD

ADC

GND

CFLT_3

–

3.1V to 34V

GND

CBYPASS

GND

OPTIONAL

RISO

RFLT_3

Figure 8-3. Example Multi-Stage Filtering Configuration for High-EMI Environments

In most applications, filtering on VDD and VOUT is sufficient to achieve good noise performance. Filtering on the

ground path is generally not required unless significant ground noise is present, as ground-path filtering can

introduce DC offsets that affect measurement accuracy.

8.1.5.2 Design Guidelines for EMI Filtering

The filtering configuration shown in Figure 8-3 illustrates a scalable approach that can be adapted based on

system noise conditions and routing requirements. At a minimum, a capacitor (CLOAD) can be placed at the VOUT

pin to provide local high-frequency filtering. Because this capacitor directly loads the output stage, the capacitor

value must be selected in accordance with the capacitive-load drive capability described in Section 7.3.2.2. In

applications without a series isolation resistor, the total effective capacitance seen at VOUT must not exceed

2.2nF.

A series isolation resistor (RISO), shown in Figure 8-3, is recommended for applications with downstream

filtering, long trace lengths, or unknown capacitive loading. When RISO is greater than or equal to 300Ω, the

output maintains a phase margin of at least 45° across the full capacitive-load range, allowing greater flexibility

in downstream filtering.

ISOTMP35R

SNIS244A – SEPTEMBER 2025 – REVISED MAY 2026

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