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M59BW102

data. DQ6 will toggle following toggling of either G,

or E when G is low. The operation is completed

when two successive reads yield the same output

data. The next read will output the bit last pro-

grammed or a ’1’ after erasing. The toggle bit DQ6

is valid only during P/E.C. operations, that is after

the fourth W pulse for programming or after the

sixth W pulse for Erase. See Figure 13 for Toggle

Bit flowchart and Figure 14 for Toggle Bit wave-

forms.

Toggle Bit (DQ2). This toggle bit, together with

DQ6, can be used to determine the device status

during the Erase operations. During Chip Erase a

read operation will cause DQ2 to toggle since chip

is being erased. DQ2 will be set to ’1’ during pro-

gram operation and when erase is complete.

Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.

when there is a failure of programming or chip

erase that results in invalid data in the memory. In

case of an error in program, the chip must be dis-

carded. The DQ5 failure condition will also appear

if a user tries to program a ’1’ to a location that is

previously programmed to ’0’. The error bit resets

after a Read/Reset (RD) instruction. In case of

success of Program or Erase, the error bit will be

set to ’0’.

Erase Timer Bit (DQ3). This bit is set to ’0’ by the

P/E.C. when the Erase command has been en-

tered to the Command Interface and it is awaiting

the Erase start. When the erase timeout period is

finished, after 50µs to 120µs, DQ3 returns to '1'.

Coded Cycles

The two Coded cycles unlock the Command Inter-

face. They are followed by an input command or a

confirmation command. The Coded cycles consist

of writing the data AAh at address 555h during the

first cycle. During the second cycle the Coded cy-

cles consist of writing the data 55h at address

2AAh. Address lines A0 to A10 are valid; other ad-

dress lines are 'don't care'. The Coded cycles hap-

pen on first and second cycles of the command

write or on the fourth and fifth cycles.

Note: 1. Commands not interpreted in this table will default to read array mode.

2. A wait of 10µs is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new

operation.

3. X = Don't Care.

4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-

mand cycles.

code.

6. For Coded cycles address inputs A11-A16 are don't care.

7. Read Data Polling, Toggle bits until Erase completes.

Mne.

Instr.

Cyc.

1st Cyc.

2nd Cyc.

3rd Cyc.

4th Cyc.

5th Cyc.

6th Cyc.

7th Cyc.

Read/Reset

Memory Array

1+

X

Read Memory Array until a new write cycle is initiated.

Data

F0h

3+

555h

2AAh

X

Read Memory Array until a new write

cycle is initiated.

Data

AAh

55h

F0h

Auto Select

3+

555h

2AAh

555h

Read Electronic Signature until a new

write cycle is initiated. See Note 5.

Data

AAh

55h

90h

PG

Program

4

555h

2AAh

555h

Program

Address

Read Data Polling or Toggle

Bit until Program completes.

Data

AAh

55h

A0h

Program

Data

CE

Chip Erase

6

555h

2AAh

555h

555h

2AAh

555h

Note 7

Data

AAh

55h

80h

AAh

55h

10h