AS7341-DLGT datasheet(24/69 Pages) AMSOSRAM

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AS7341

I²C Interface

Datasheet

• PUBLIC

DS000504

• v3-00 • 2020-Jun-25

│ 23

9.3

I²C Read Transaction

A Read transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS,

RESTART, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP. Following all but the final byte the

master places an ACK on the bus (9TH clock pulse). Termination of the Read transaction is indicated

by a NACK being placed on the bus by the master, followed by STOP.

Figure 29:

2C Read

9.4

Timing Characteristics

Figure 30:

I²C Timing Characteristics

Symbol

Parameter

Min

Typ

Max

Unit

fSCL

I²C clock frequency

400

kHz

tBUF

Bus free time between start and stop

condition

1.3

µs

tHS;STA

Hold time after (repeated) start condition.

After this period, the first clock is generated.

0.6

µs

tSU;STA

Repeated start condition setup time

0.6

µs

tSU;STO

Stop condition setup time

0.6

µs

tLOW

SCL clock low period

1.3

µs

tHIGH

SCL clock high period

0.6

µs

tHD;DAT

Data hold time

tSU;DAT

Data setup time

100

Clock/data fall time

300

Clock/data rise time

300

A Sr

data

RA++

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