AS7341-DLGT datasheet(34/69 Pages) AMSOSRAM

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AS7341

Datasheet

• PUBLIC

DS000504

• v3-00 • 2020-Jun-25

│ 33

ASTEP Register (Address 0xCA, 0xCB)

Figure 41:

ASTEP Register

Addr: 0xCA, 0xCB

ASTEP

Bit

Bit Name

Default

Access

Bit Description

7:0

ASTEP 0xCA

999

Integration time step size.

Sets the integration time per step in increments of

2.78µs. The default value is 999.

VALUE

STEP SIZE

2.78µs

2.78µs x (n+1)

15:8

ASTEP 0xCB

599

1.67ms

999

2.78ms

17999

50ms

65534

182ms

65535

reserved, do not use

WTIME Register (Address 0x83)

If wait is enabled (WEN = “1” register 0x80), each new measurement is started based on WTIME. It is

necessary for WTIME to be sufficiently long for spectral integration and any other functions to be

completed within the period. The device will warn the user if the timing is configured incorrectly. If

WTIME is too short, then SP

_TRIG in register STATUS6 (ADDR: 0xA7) will be set to “1”.

Figure 42:

WTIME Register

Addr: 0x83

WTIME

Bit

Bit Name

Default

Access

Bit Description

7:0

WTIME

0x00

Spectral Measurement Wait time.

8-bit value to specify the delay between two

consecutive spectral measurements.

Value

Wait Cycles

Wait Time

0x00

2.78ms

0x01

5.56ms

2.78ms x (n+1)

0xff

256

711ms

AS7341-DLGT Datasheet(PDF) 34 Page - ams-OSRAM AG

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