CMV300 datasheet(51/56 Pages) AMSOSRAM

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Reference:CMV300-datasheet-v2.11

CMV300 Datasheet

Page 49 of 54

10 SPECIFICATION OVERVIEW

Specification

Value

Comment

Effective pixels

648 x 488

Containing 4 dark reference columns and rows.

Pixel pitch

7.4 x 7.4 µm2

Optical format

1/3”

Full well charge

20 Ke-

Pinned photodiode pixel.

Conversion gain

0.185LSB/e-

12 bit mode, unity gain

Sensitivity

6 V/lux.s

With microlenses @ 550nm

Temporal noise

(analog domain)

20 e-

Pipelined global shutter (GS) with correlated

double sampling ( CDS )

Dynamic range

60 dB

Pixel type

Global shutter

pixel

Allows fixed pattern noise correction and reset

(kTC) noise canceling through correlated

double sampling.

Shutter type

Pipelined global

shutter

Exposure of next image during readout of the

previous image.

Parasitic light

sensitivity -

Shutter efficiency

<1/50 000

>99.998%

Color filters

Optional

RGB Bayer pattern

Micro lenses

Yes

QE * FF

55%

@ 550 nm with micro lenses.

Dark current

signal

125 e/s

@ 25C die temperature

DSNU

12 LSB/s

12 bit mode

Fixed pattern

noise

<4 LSB RMS

<0.1% of full swing, 12 bit mode

PRNU

< 1% RMS of

signal

LVDS Output

channel

Each data output running @ 300 Mbit/s.

2 and 1 outputs selectable at reduced frame

rate.

Parallel CMOS output available

Frame rate

480 frames/s

Using a 12bit/pixel and 480 Mbit/s LVDS

output. Higher frame rate possible in row

windowing mode.

Timing generation

On-chip

Possibility to control exposure time through

external pin.

PGA

Yes

4 analog gain settings

Programmable

Registers

Sensor

parameters

Window coordinates, Timing parameters, Gain

& offset, Exposure time, flipped readout in x

and y direction …

Supported HDR

modes

Interleaved

integration times

Piecewise linear

response

Interleaved exposure times for different

columns: Odd columns (double rows for color)

have a different exposure compared to even

columns (double columns for color). Final

image is a combination of the two (through

interpolation).

Response curve with two kneepoints

ADC

12bit

Column ADC

Interface

LVDS or CMOS

parallel

Serial output data + synchronization signals

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