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RX72N Datasheet(PDF) 102 Page - Renesas Technology Corp |
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RX72N Datasheet(HTML) 102 Page - Renesas Technology Corp |
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102 / 179 page  R01DS0343EJ0120 Rev.1.20 Page 102 of 179 Nov 15, 2023 RX72N Group 2. Electrical Characteristics 2.4.5 Bus Timing Table 2.26 Bus Timing Conditions 1: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, ICLK = 8 to 240 MHz, PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the drive capacity control register. Conditions 2: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 3.0 to 3.6 V, 3.0 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, ICLK = 60 to 240 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, 60 MHz < BCLK = SDCLK ≤ 80 MHz, Ta =Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 15 pF for the SDCLK pin, C = 30 pF for other pins. To control the drive capacity when using the SDRAM: set the PFBCR3.SDCLKDRV bit in external bus control register 1 to 1 to select the drive capacity of the SDCLK pin, and set the SDRAM pins other than the SDCLK pin as high- speed-interface driving outputs. Item Symbol Conditions 1 Conditions 2 Unit Test Conditions Min. Max. Min. Max. Address delay time tAD — 12.5 — 12.5 ns Figure 2.18 to Figure 2.23 Byte control delay time tBCD — 12.5 — 12.5 ns CS# delay time tCSD — 12.5 — 12.5 ns ALE delay time tALED — 12.5 — 12.5 ns RD# delay time tRSD — 12.5 — 12.5 ns Read data setup time tRDS 12.5 — 12.5 — ns Read data hold time tRDH 0— 0 — ns WR# delay time tWRD — 12.5 — 12.5 ns Write data delay time tWDD — 12.5 — 12.5 ns Write data hold time tWDH 0— 0 — ns WAIT# setup time tWTS 12.5 — 12.5 — ns Figure 2.24 WAIT# hold time tWTH 0— 0 — ns Address delay time 2 (SDRAM) tAD2 1 12.5 1 10.0 ns Figure 2.25 to Figure 2.31 CS# delay time 2 (SDRAM) tCSD2 1 12.5 1 10.0 ns DQM delay time (SDRAM) tDQMD 1 12.5 1 10.0 ns CKE delay time (SDRAM) tCKED 1 12.5 1 10.0 ns Read data setup time 2 (SDRAM) tRDS2 10 — 6.0 — ns Read data hold time 2 (SDRAM) tRDH2 0— 0 — ns Write data delay time 2 (SDRAM) tWDD2 — 12.5 — 10.0 ns Write data hold time 2 (SDRAM) tWDH2 1— 1 — ns WE# delay time (SDRAM) tWED 1 12.5 1 10.0 ns RAS# delay time (SDRAM) tRASD 1 12.5 1 10.0 ns CAS# delay time (SDRAM) tCASD 1 12.5 1 10.0 ns |
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