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RX72N Datasheet(PDF) 124 Page - Renesas Technology Corp |
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RX72N Datasheet(HTML) 124 Page - Renesas Technology Corp |
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124 / 179 page ![]() R01DS0343EJ0120 Rev.1.20 Page 124 of 179 Nov 15, 2023 RX72N Group 2. Electrical Characteristics 2.4.7.8 GPTW Note 1. tPAcyc: PCLKA cycle Note 2. tPBcyc: PCLKB cycle Figure 2.52 GPTW Input Capture Input Timing Figure 2.53 GPTW External Trigger Input Timing Table 2.35 GPTW Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the drive capacity control register. Item Symbol Min. Max. Unit*1, *2 Test Conditions GPTW Input capture input pulse width Single-edge setting tGTICW 1.5 — tPAcyc Figure 2.52 Both-edge setting 2.5 — External trigger input pulse width Single-edge setting tGTEW 1.5 — tPBcyc Figure 2.53 Both-edge setting 2.5 — Input capture input PCLKA tGTICW GTETRGn input (n = A to D) PCLKB tGTEW |
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