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RZ/A3UL Datasheet(PDF) 40 Page - Renesas Technology Corp |
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RZ/A3UL Datasheet(HTML) 40 Page - Renesas Technology Corp |
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40 / 69 page ![]() RZ/A3UL Group 3. Electrical Characteristics R01DS0487EJ0110 Rev.1.10 Page 40 of 69 Jun 16, 2025 3.5.7 JTAG Debugger Interface Access Timing Table 3.34 Debugger IF Timing Item Symbol Min. Max. Unit Figures TCK_SWCLK cycle time tTCKcyc 50 — ns Figure 3.22 TCK_SWCLK high pulse width tTCKH 20 — ns Figure 3.23 TCK_SWCLK low pulse width tTCKL 20 — ns TDI setup time tTDIS 15 — ns TDI hold time tTDIH 15 — ns TMS_SWDIO setup time tTMSS 15 — ns TMS_SWDIO hold time tTMSH 15 — ns SWDIO delay time tSWDO — 14 ns TDO delay time tTDOD — 14 ns Capture register setup time tCAPTS 10 — ns Figure 3.24 Capture register hold time tCAPTH 10 — ns Update register delay time tUPDATED — 20 ns 1/2 JTAG_PVDD tTCKcyc tTCKH tTCKL VIH VIH VIL VIL VIH 1/2 JTAG_PVDD Figure 3.22 TCK_SWDCLK Input Timing |
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