RZSLASHA3UL datasheet(2/69 Pages) RENESAS

2 / 69 page

RZ/A3UL Group

1. Overview

R01DS0487EJ0110 Rev.1.10

Page 2 of 69

Jun 16, 2025

Overview

1.1

Outline of Specification

1.1.1

CPU Core

Item

Description

System CPU Cortex-A55

[RZ/A3UL]

● Arm Cortex-A55 Single MPCore 1.0 GHz

● L1 I-cache 32 Kbytes (Parity) / D-cache 32 Kbytes (ECC)

● L2 cache 0 Kbyte

● L3 cache 256 Kbytes (ECC)

● Arm® NEON™ / FPU supported

● Cryptographic Extension supported

● Arm® v8.2-A architecture

Boot

[RZ/A3UL]

● 6 boot modes

Boot Mode 0: Booting from eSD

Boot Mode 1: Booting from eMMC (1.8 V)

Boot Mode 2: Booting from eMMC (3.3 V)

Boot Mode 3: Booting from a serial flash memory (Single / Quad / Octa) connected to the

SPI Multi I/O or Octa I/F bus space (1.8 V)

Boot Mode 4: Booting from a serial flash memory (Single / Quad) connected to the SPI Multi

I/O bus space (3.3 V)

Boot Mode 5: Booting from SCIF download

Note: Boot Mode 0, 1, 2 and 5 are not supported.

Debug Interface

[RZ/A3UL]

● Arm® CoreSight™ architecture

● JTAG / SWD interface supported

● ETF 16 Kbytes for program flow trace (each cluster)

● JTAG Disable supported

RZ/A3UL Datasheet(PDF) 2 Page - Renesas Technology Corp