RZSLASHT2ME datasheet(89/116 Pages) RENESAS

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2.5.5.11

SPI Timing

Table 2.35

SPI timing (1 of 2)

Conditions: VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 30 pF

Parameter

Symbol

Min.*1

Max.*1

Unit*1

Reference

figure

RSPCK clock cycle

Master

tSPcyc

4096

tSPIcyc Figure 2.65

Slave

4096

RSPCK clock high level pulse width

Master

tSPCKWH

(tSPcyc − tSPCKr −

tSPCKf) / 2 − 2.5

—

Slave

—

tSPIcyc

RSPCK clock low level pulse width

Master

tSPCKWL

(tSPcyc − tSPCKr −

tSPCKf) / 2 − 2.5

—

Slave

—

tSPIcyc

RSPCK clock rising/falling time

Output

tSPCKr,

tSPCKf

—

Input

—

Data input setup time

Master

tSU

—

Figure 2.66 to

Figure 2.72

Slave

—

Data input hold time

Master

—

Slave

—

SSL setup time

Master

tLEAD

N × tSPcyc − 3*2

N × tSPcyc + 3*2

Figure 2.66 to

Figure 2.69

Slave

—

tSPIcyc

SSL hold time

Master

tLAG

N × tSPcyc − 3*3

N × tSPcyc + 3*3

Slave

—

tSPIcyc

Continuous transmission delay

Master

tTD

tSPcyc + 2 × tSPIcyc

8 × tSPcyc + 2 ×

tSPIcyc

Slave

tSPcyc + 5 × tSPIcyc

—

TI-SSP SS input setup time

tTISS

—

Figure 2.70 to

Figure 2.72

TI-SSP SS input hold time

tTISH

—

TI-SSP next access time

tTIND

M*4

—

tSPIcyc

TI-SSP Master SS output delay

tTISSOD

-3

TI-SSP Master OE delay 1

tTIMOED1

—

TI-SSP Master OE delay 2

tTIMOED2

—

TI-SSP Slave OE delay 1

tTISOED1

—

TI-SSP Slave OE delay 2

tTISOED2

—

Data output delay time

Master

tOD

—

Figure 2.66 to

Figure 2.72

Slave

—

Data output hold time

Master

tOH

-3

—

Slave

—

MOSI, MISO rising/falling time

Output

tDr, tDf

—

Input

—

µs

SSL rising/falling time

Output

tSSLr, tSSLf

—

Figure 2.66,

Figure 2.67

Input

—

µs

RZ/T2ME Datasheet

2. Electrical Characteristics

R01DS0441EJ0110 Rev.1.10

Mar 13, 2026

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