MK50H25 datasheet(14/64 Pages) STMICROELECTRONICS

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SECTION 4

PROGRAMMING SPECIFICATION

This section defines the Control and Status Reg-

isters and the memory data structures required to

program the MK50H25.

4.1 Control and Status Registers

There are six Control and Status Registers

(CSR’s) resident within the MK50H25.

The

CSR’s are accessed through two bus address-

able ports, an address port (RAP), and a data

port (RDP), thus requiring only two locations in

the system memory or I/O map.

4.1.1 Accessing the Control & Status Registers

The CSR’s are read (or written) in a two step op-

eration. The address of the CSR is written into the

address port (RAP) during a bus slave transac-

tion. During a subsequent bus slave transaction,

the data being read from (or written into) the data

port (RDP) is read from (or written into) the CSR

selected in the RAP. Once written, the address in

RAP remains unchanged until rewritten or upon a

bus reset. A control I/O pin (ADR) is provided to

distinguish the address port from the data port.

ADR

Port

L Register Data Port (RDP)

H Register Address Port (RAP)

4.1.1.1 Register Address Port (RAP)

0000

CSR

<2:0>

BIT

NAME

DESCRIPTION

15:08

RESERVED

Must be written as zeroes

BM8

When set, places chip into 8 bit mode. CSR’s, Init Block, and data transfers are all 8 bit

transfers; this provides compatibility with 8 bitmicroprocessors. When clear, all transfers

are 16 bit transfers. This bit must be set to the same value each time it is written,

changing this bit during normal operation will achieve unexpected results. BM8 is

READ/WRITE and cleared on Bus RESET.

06:04

RESERVED

Must be written as zeroes

03:01

CS3<2:0>

CSR address select bits. READ/WRITE. Selects the CSR to be accessed through the

RDP. RAP is cleared by Bus RESET.

CSR<2:0>

CSR

CSR0

CSR1

CSR2

CSR3

CSR4

CSR5

HBYTE

Determines which byte is addressed for 8 bit mode. If set, the high byte of the register

referred to by CSR<2:0> is addressed, otherwise the low byte is addressed. This bit is

only meaningful in 8 bit mode and must be written as zero if BM8=0. HBYTE is

READ/WRITE and cleared on bus reset.

MK50H25

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