MK50H25PLCC datasheet(10/64 Pages) STMICROELECTRONICS

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FWM of being full (by DMA from TX buffer in

shared memory), the transmit FIFO will not inter-

rupt the microcontroller until it empties enough to

fall below the watermark level.

The transmit FIFO also has a selectable Transmit

Hold-Off watermark mechanism to determine

when data transmission will begin once data has

been put in the transmit FIFO.

The Transmit

Hold-Off watermark is enabled by setting bit 10

(XHOLD) in CSR4. The selection of FWM (FIFO

WaterMark) also in CSR4 determines corre-

sponding appropriate values of Transmit Hold-Off

so that the device cannot be inadvertently pro-

grammed to have conflicting watermarks.

For

FWM settings of 9, 17, and 25 words, the Trans-

mit Hold-Off watermarks are 19, 11, and 3 words

respectively.

For example, if FWM is set at 9 words and the

Transmit Hold-Off watermark is enabled, the

MK50H25 will not begin transmitting until more

than 19 words have been placed in the Transmit

FIFO or an end-of-frame has been transmitted.

This greatly reduces the chances of Transmitter

Underrun that could be possible at high data rates

(ie: TCLK > 0.15 x SYSCLK) if Transmit Hold-Off

is not selected (causing transmission to begin as

soon as 1 byte is transferred to the TX FIFO).

3.1.7 DMA Controller

The MK50H25 has an on-chip DMA Controller cir-

cuit. This allows it to access memory without re-

quiring host software intervention. Whenever the

MK50H25 requires access to the host memory it

will negotiate for mastership of the bus.

Upon

gaining control of the bus the MK50H25 will begin

transferring data to or from memory.

The

MK50H25 will perform memory transfers until

either it has nothing more to transfer, it has

reached its DMA burst limit (user programmable),

or the BUSREL pin is driven low. In any case, it

will complete all bus transfers before releasing

bus mastership back to the host.

If during a

memory transfer, the memory does not respond

within 256 SCLK cycles, the MK50H25 will re-

lease ownership of the bus immediately and the

MERR bit will be set in CSR0. The DMA burst

limit can be programmed by the user through

CSR4. In 16 bit mode the limit can be set to 1

word, 8 words, or unlimited word transfers. In 8

bit mode,it can be set to 2 bytes, 16 bytes, or un-

limited byte transfers. For high speed data lines

(i.e. > 1 Mbps) a burst limit of 8 words or 16 bytes

is suggested to allow maximum throughput.

The byte ordering of the DMA transfers can be

programmed to account for differences in proces-

sor architectures or host programming languages.

Byte ordering can be programmed separately for

data and control information. Data information is

defined as all contents of data buffers; control in-

formation is defined as anything else in the

shared memory space (i.e. initialization block, de-

scriptors, etc). For more information see section

4.1.2.5 on control status register 4.

3.1.8 Bus Slave Circuitry

The MK50H25 contains a bank of internal con-

trol/status registers (CSR0-5) which can be ac-

cessed by the host as a peripheral. The host can

read or write to these registers like any other bus

slave. The contents of these registers are listed

in Section 4 and bus signal timing is described in

Figures 9 and 10.

3.2 Buffer Management Overview

Refer to Fig. 3.

3.2.1 Initalization Block

Chip initialization information is located in a block

of memory called the Initialization Block. The In-

itialization Block consists of 25 contiguous words

of memory starting on a word boundary.

This

memory is assembled by the HOST, and is ac-

cessed by the MK50H25 during initialization. The

Initialization Block is comprised of:

A. Mode of Operation.

B. Frame Address Values.

C. N1 Counter (Max Frame Length) Value.

D. Timer Preset Values

E. Location and size of Receive and Transmit De-

scriptor Rings.

F. Location and size of XID/TEST Buffers.

G. Location of Status Buffer.

H. Error Counters.

3.2.2 The Circular Queue

The basic organization of the buffer management

is a circular queue of tasks in memory called de-

scriptor rings. There are separate rings to de-

scribe the transmit and receive operations. Up to

128 buffers may be queued-up on a descriptor

ring awaiting execution by the MK50H25.

The

descriptor ring has a descriptor assigned to each

buffer. Each descriptor holds a pointer for the

starting address of the buffer, and holds a value

for the length of the buffer in bytes.

Each descriptor also contains two control bits

called OWNA and OWNB, which denote whether

the MK50H25, the HOST, or the I/O ACCELERA-

TION PROCESSOR ( if present ) ”owns” the buff-

er. For transmit, when the MK50H25 owns the

buffer, the MK50H25 is allowed and commanded

to transmit the buffer. When the MK50H25 does

not own the buffer, it will not transmit that buffer.

For receive, when the MK50H25 owns a buffer, it

may place received data into that buffer. Con-

versely, when the MK50H25 does not own a re-

ceive buffer, it will not place received data into

that buffer.

The MK50H25 buffer management mechanism

will handle frames which are longer than the

length of an individual buffer. This is done by a

chaining method which utilizes multiple buffers.

The MK50H25 tests the next descriptor in the de-

MK50H25

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