MK50H25PLCC datasheet(16/64 Pages) STMICROELECTRONICS

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4.1.2 Control and Status Register Definition

4.1.2.1 Control and Status Register 0 (CSR0)

RAP<3:1> = 0

BIT

NAME

DESCRIPTION

TDMD

TRANSMIT DEMAND, when set, causes the MK50H25 access the

Transmit Descriptor Ring without waiting for the Transmit poll time in-

terval to lapse. TDMD need not be set to transmit a frame, it merely

hastens the MK50H25’s response to a Transmit Descriptor Ring entry

insertion by the host. TDMD is written with ONE ONLY and cleared by

the MK50H25 microcode after it is used. It may read as a ”1” for a

short time after it is written because the microcode may have been

busy when TDMD was set. It is also cleared by Bus RESET. Writing a

”0” in this bit has no effect.

STOP

STOP, when set, indicates that MK50H25 is operating in the Stopped

phase of operation. All external activity is disabled and internal logic is

reset. MK50H25 remains inactive except for primitive processing until

a START primitive is issued. STOP IS READ ONLY and set by Bus

RESET or a STOP primitive. Writing to this bit has no effect.

DTX

Disable Transmitter ring prevents the MK50H25 from further access to

the Transmitter Descriptor Ring. No transmissions are attempted after

finishing transmission of any frame in transmission at the time of DTX

being set. TXON acknowledges changes to DTX, see below. DTX is

READ/WRITE.

DRX

Disable the Receiver prevents the MK50H25 from further access to the

Receiver Descriptor Ring. No received frames are accepted after fin-

ishing reception of any frame in reception at the time of DRX being set.

If DRX is set while a data link is established, the MK50H25 will go into

the Local Busy state and will send an RNR response frame to the re-

mote station. Upon clearing DRX the MK50H25 will send a RR re-

sponse frame. RXON acknowledges changes to DRX, see description

of RXON. DRX is READ/WRITE.

TXON

TRANSMITTER ON indicates that the transmit ring access is enabled.

TXON is set as the Start primitive is issued if the DTX bit is ”0” or after-

ward as DTX is cleared. TXON is cleared upon recognition of DTX be-

ing set, by sending a Stop primitive in CSR1, or by a Bus RESET. If

TXON is clear, the host may modify the Transmit Descriptor Ring en-

tries regardless of the state of the OWNA bits. TXON is READ ONLY;

writing to this bit has no effect.

RXON

RECEIVER ON indicates that the receive ring access is enabled.

RXON is set as the Start primitive is issued if the DRX bit is ”0” or after-

ward as DRX is cleared.

RXON is cleared upon recognition of DRX

being set, by sending a Stop primitive in CSR1, or by a Bus RESET. If

RXON is clear, the host may modify the Receive Descriptor Ring en-

tries regardless of the state of the OWNA bits. RXON is READ ONLY;

writing to this bit has no effect.

MK50H25

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