MSP430F5437AIPN datasheet(13/88 Pages) TI

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Interrupt Vector Addresses

MSP430F543x, MSP430F541x

MSP430F543xA, MSP430F541xA

www.ti.com ...................................................................................................................................................................................................... SLAS609 – JUNE 2008

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Interrupt Sources, Flags, and Vectors

SYSTEM

WORD

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

INTERRUPT

ADDRESS

System Reset

Power-Up

External Reset

WDTIFG, KEYV (SYSRSTIV)(1)(2)

Reset

0FFFEh

63, highest

Watchdog Timeout, Key Violation

Flash Memory Key Violation

System NMI

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

PMM

VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,

(Non)maskable

0FFFCh

Vacant Memory Access

JMBOUTIFG (SYSSNIV)(1)

JTAG Mailbox

User NMI

NMI

NMIIFG, OFIFG, ACCVIFG (SYSUNIV)(1)(2)

(Non)maskable

0FFFAh

Oscillator Fault

Flash Memory Access Violation

Timer_B7

TBCCR0 CCIFG0 (3)

Maskable

0FFF8h

TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,

Timer_B7

Maskable

0FFF6h

TBIFG (TBIV)(1)(3)

Watchdog Timer_A Interval Timer

WDTIFG

Maskable

0FFF4h

Mode

USCI_A0 Receive/Transmit

UCA0RXIFG, UCA0TXIFG (UCA0IV)(1)(3)

Maskable

0FFF2h

USCI_B0 Receive/Transmit

UCB0RXIFG, UCB0TXIFG (UCAB0IV)(1)(3)

Maskable

0FFF0h

ADC12_A

ADC12IFG0 ... ADC12IFG15 (ADC12IV)(1)(3)

Maskable

0FFEEh

Timer0_A5

TA0CCR0 CCIFG0(3)

Maskable

0FFECh

TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,

Timer0_A5

Maskable

0FFEAh

TA0IFG (TA0IV)(1)(3)

USCI_A2 Receive/Transmit

UCA2RXIFG, UCA2TXIFG (UCA2IV)(1)(3)

Maskable

0FFE8h

USCI_B2 Receive/Transmit

UCB2RXIFG, UCB2TXIFG (UCB2IV)(1)(3)

Maskable

0FFE6h

DMA

DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1)(3)

Maskable

0FFE4h

Timer1_A3

TA1CCR0 CCIFG0(3)

Maskable

0FFE2h

TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,

Timer1_A3

Maskable

0FFE0h

TA1IFG (TA1IV)(1)(3)

I/O Port P1

P1IFG.0 to P1IFG.7 (P1IV)(1)(3)

Maskable

0FFDEh

USCI_A1 Receive/Transmit

UCA1RXIFG, UCA1TXIFG (UCA1IV)(1)(3)

Maskable

0FFDCh

USCI_B1 Receive/Transmit

UCB1RXIFG, UCB1TXIFG (UCB1IV)(1)(3)

Maskable

0FFDAh

USCI_A3 Receive/Transmit

UCA3RXIFG, UCA3TXIFG (UCA3IV)(1)(3)

Maskable

0FFD8h

USCI_B3 Receive/Transmit

UCB3RXIFG, UCB3TXIFG (UCB3IV)(1)(3)

Maskable

0FFD6h

I/O Port P2

P2IFG.0 to P2IFG.7 (P2IV)(1)(3)

Maskable

0FFD4h

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RTC_A

Maskable

0FFD2h

RT0PSIFG, RT1PSIFG (RTCIV)(1)(3)

0FFD2h

Reserved

Reserved(4)

⋮

0FF80h

0, lowest

(1)

Multiple source flags

(2)

A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(3)

Interrupt flags are located in the module.

(4)

Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain

compatibility with other devices, it is recommended to reserve these locations.

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