R31DS0112EU0108 Rev.1.08

Page 23

Jun 5, 2026

9FGL02x1/04x1/06x1/08x1D Datasheet

Table 21. Byte 0: Output Enable Register

Byte 0 [1]

1. A low on these bits will override the OE# pin and force the differential output to the state indicated by B11[1:0] (Low/Low default)

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Control

Function

Output

Enable

Output

Enable

Output

Enable

Output

Enable

Output

Enable

Output

Enable

Output

Enable

Output

Enable

Type

RW

RW

RW

RW

RW

RW

RW

RW

0

See B11[1:0]

1

OE# Pin Controls Output

9FGL08

Name

OE7

OE6

OE5

OE4

OE3

OE2

OE1

OE0

9FGL08

Default

1

1

1

1

1

1

1

1

9FGL06

Name

OE5

OE4

Reserved

OE3

OE2

OE1

Reserved

OE0

9FGL06

Default

1

1

x

1

1

1

x

1

9FGL04

Name

Reserved

Reserved

Reserved

Reserved

OE3

OE2

OE1

OE0

9FGL04

Default

x

x

x

x

1

1

1

1

9FGL02

Name

Reserved

Reserved

Reserved

Reserved

Reserved

OE1

OE0

Reserved

9FGL02

Default

x

x

x

x

x

1

1

x

Table 22. Byte 1: Spread Spectrum with VHIGH Control Register

Byte 1

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Control

Function

SS Enable

Readback

Bit1

SS Enable

Readback

Bit0

Enable software

control of spread

spectrum

SS Software

Control Bit1

SS Software

Control Bit0

Reserved

Controls

Output

Amplitude

Type

R

R

RW

RW [1]

1. See notes on Spread and Mode Selection table. B1[5] must be set to a 1 in order to use B1[4:3].

RW [1]

RW

RW

0

See Spread and Mode

Selection table

SS controlled by

latch (B1[7:6])

See Spread and Mode

Selection table

00 = 0.6V

10 = 0.75V

1

Values in B1[4:3]

control SS amount

01 = 0.68V

11 = 0.85V

Name

SSENRB1

SSENRB1 SSEN_SWCNTRL SSENSW1

SSENSW0

AMPLITUDE

1

AMPLITUDE

0

Default

Latch

Latch

0

0

0

x

1

0