TSB21LV03

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS230A – MARCH 1996 – REVISED DECEMBER 1996

2

POST OFFICE BOX 655303

description (continued)

Data bits to be transmitted through the cable ports are received from the LLC on two or four data lines (D0 –

D3), and are latched internally in the TSB21LV03 in synchronization with the 49.152-MHz system clock. These

bits are combined serially, encoded, and transmitted at 98.304 or 196.608 Mbits/s as the outbound data-strobe

information stream. During transmission, the encoded data information is transmitted differentially on the TPB

cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s).

During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers

for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded

Strobe information is received on the TPB cable pair. The received data-strobe information is decoded to

recover the receive clock signal and the serial data bits. The serial data bits are split into two or four parallel

streams, resynchronized to the local system clock, and sent to the associated LLC. The received data is also

transmitted (repeated) out of the other active (connected) cable ports.

Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during

initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the

arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this

common mode voltage is used during arbitration to set the speed of the next packet transmission. In addition,

the TPB channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied

twisted-pair bias voltage. The presence or absence of this common-mode voltage is used as an indication of

cable connection status. The cable connection status signal is internally debounced in the TSB21LV03 on a

cable disconnect-to-connect. The debounced cable connection status signal initiates a bus reset. On a cable

disconnect-to-connect a debounce delay is incorporated. There is no delay on a cable disconnect.

The TSB21LV03 provides a 1.86 V nominal bias voltage for driver load termination. This bias voltage, when seen

through a cable by a remote receiver, indicates the presence of an active connection. The value of this bias

voltage has been chosen to allow interoperability between transceiver chips operating from either 5-V or 3-V

nominal supplies. This bias voltage source should be stabilized by using an external filter capacitor of

approximately 1.0

µF.

The transmitter circuitry is disabled under the following conditions: power down, cable not active, reset, or

transmitter disable. The receiver circuitry is disabled under the following conditions: power down, cable not

active, or receiver disable. The twisted-pair bias voltage circuitry is disabled under the following conditions:

power down or reset. The power-down condition occurs when the PD input is high. The cable-not-active (CNA)

condition occurs when the cable connection status indicates that no cable is connected. The reset condition

occurs when the RESET input terminal is low. The transmitter disable and receiver disable conditions are

determined from the internal logic.

The line drivers in the TSB21LV03 operate in a high-impedance current mode and are designed to work with

external 112-

Ω line-termination resistor networks. One network is provided at each end of each twisted-pair

cable. Each network is composed of a pair of series-connected 56-

Ω resistors. The midpoint of the pair of

resistors that is directly connected to the twisted-pair A (TPA) package terminals is connected to the TPBIAS

voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B (TPB)

package terminals is coupled to ground through a parallel RC network with recommended resistor and capacitor

values of 5 K

Ω and 250 pF respectively. The values of the external resistors are designed to meet the draft

standard specifications when connected in parallel with the internal receiver circuits and are shown in Figure 3.

The driver output current, along with other internal operating currents, is set by an external resistor. This resistor

is connected between the R0 and R1 terminals and has a value of 6.3 k

Ω, ±0.5%.