HT46R46 datasheet(28/77 Pages) HOLTEK

28 / 77 page

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.30

June 5, 2008

The ADCR control register also contains the

PCR2~PCR0 bits which determine which pins on Port B

are used as analog inputs for the A/D converter and

which pins are to be used as normal I/O pins. If the 3-bit

address on PCR2~PCR0 has a value of

²100² or higher,

then all four pins, namely AN0, AN1, AN2 and AN3 will all

be set as analog inputs. Note that if the PCR2~PCR0 bits

are all set to zero, then all the Port B pins will be setup as

normal I/Os and the internal A/D converter circuitry will be

powered off to reduce the power consumption.

The START bit in the ADCR register is used to start and

reset the A/D converter. When the microcontroller sets

this bit from low to high and then low again, an analog to

digital conversion cycle will be initiated. When the

START bit is brought from low to high but not low again,

the EOCB bit in the ADCR register will be set to a

²1²

and the analog to digital converter will be reset. It is the

START bit that is used to control the overall on/off opera-

tion of the internal analog to digital converter.

The EOCB bit in the ADCR register is used to indicate

when the analog to digital conversion process is com-

plete. This bit will be automatically set to

²0² by the

microcontroller after a conversion cycle has ended. In

addition, the corresponding A/D interrupt request flag

will be set in the interrupt control register, and if the inter-

rupts are enabled, an appropriate internal interrupt sig-

nal will be generated. This A/D internal interrupt signal

will direct the program flow to the associated A/D inter-

nal interrupt address for processing. If the A/D internal

interrupt is disabled, the microcontroller can be used to

poll the EOCB bit in the ADCR register to check whether

it has been cleared as an alternative method of detect-

ing the end of an A/D conversion cycle.

A/D Converter Clock Source Register - ACSR

The clock source for the A/D converter, which originates

from the system clock fSYS, is first divided by a division

ratio, the value of which is determined by the ADCS1

and ADCS0 bits in the ACSR register.

Although the A/D clock source is determined by the sys-

tem clock fSYS, and by bits ADCS1 and ADCS0, there are

some limitations on the maximum A/D clock source speed

that can be selected. As the minimum value of permissible

A/D clock period, tAD,is0.5

ms for the HT46R46, device,

and 1

ms for the other devices, care must be taken for sys-

tem clock speeds in excess of 2MHz. With the exception of

the HT46R46 device, for system clock speeds in excess of

2MHz, the ADCS1 and ADCS0 bits should not be set to

²00². For the HT46R46 device, for system clock speeds in

excess of 4MHz, the ADCS1 and ADCS0 bits should not

be set to

²00². Doing so will give A/D clock periods that are

less than the minimum A/D clock period which may result

in inaccurate A/D conversion values. Refer to the following

table for examples, where values marked with an asterisk

* show where, depending upon the device, special care

must be taken, as the values may be less than the speci-

fied minimum A/D Clock Period.

A D C R R e g i s t e r

S e l e c t A / D c h a n n e l

b 7

b 0

S T A R T

P C R 2 P C R 1 P C R 0 A C S 2 A C S 1 A C S 0

A C S 1

A C S 2

A C S 0

: A N 0

: A N 1

: A N 2

: A N 3

: u n d e f i n e d , m u s t n o t b e u s e d

P o r t B A / D c h a n n e l c o n f i g u r a t i o n s

P C R 2

P C R 1

P C R 0

: P o r t B A / D c h a n n e l s - a l l o f f

: P B 0 e n a b l e d a s A N 0

: P B 0 ~ P B 1 e n a b l e d a s A N 0 ~ A N 1

: P B 0 ~ P B 2 e n a b l e d a s A N 0 ~ A N 2

: P B 0 ~ P B 3 e n a b l e d a s A N 0 ~ A N 3

E n d o f A / D c o n v e r s i o n f l a g

1 : n o t e n d o f A / D c o n v e r s i o n - A / D c o n v e r s i o n w a i t i n g o r i n p r o g r e s s

0 : e n d o f A / D c o n v e r s i o n - A / D c o n v e r s i o n e n d e d

S t a r t t h e A / D c o n v e r s i o n

0 ® 1 ® 0 : S t a r t

0 ® 1 : R e s e t A / D c o n v e r t e r a n d s e t E O C B t o " 1 "

E O C B

A/D Converter Control Register

A C S R R e g i s t e r

S e l e c t A / D c o n v e r t e r c l o c k s o u r c e

b 7

b 0

T E S T

A D C S 1 A D C S 0

A D C S 1

A D C S 0

: s y s t e m c l o c k / 2

: s y s t e m c l o c k / 8

: s y s t e m c l o c k / 3 2

: u n d e f i n e d

N o t i m p l e m e n t e d , r e a d a s " 0 "

F o r t e s t m o d e u s e o n l y

A/D Converter Clock Source Register

HT46R46 Datasheet(PDF) 28 Page - Holtek Semiconductor Inc

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