When set to 1, transmit deferral is enabled.

Effective only when the TX__FIFO is enabled.

B4

IR__PLS – Send Interaction Pulse.

This bit is effective only in MIR and FIR Modes.

It is set to 1 by writing 1 into it.

Writing 0 into it has no effect.

When set to 1,a2µs infrared interaction pulse is transmitted at the end of the frame and the bit is automatically cleared

by the hardware.

This bit is also cleared when the transmitter is soft reset.

Note: The interaction pulse must be emitted at least once every 500 ms, as long as the high-speed connection lasts, in order to quiet slower (115.2 kbps

or below) systems that might otherwise interfere with the link.

B7–5 MDSL [2–0] – Mode Select.

These bits are used to select the operational mode as shown in

Table 5.

When the mode is changed, the transmitter and receiver are soft reset, and the modem status events are cleared.

TABLE 5. UIR Module Operational Modes

Bits

Operational Mode

765

000

UART

001

Reserved

010

Sharp-IR

011

SIR

100

MIR

101

FIR

110

CEIR

111

Reserved

3.1.6 LSR – Link Status Register

This register provides status information to the CPU concerning the data transfer.

Bits 1 through 4 (and 7 when in MIR or FIR mode) indicate link status events.

These bits are sticky, and accumulate any conditions occurred since the last time the register was read.

These bits are cleared when any of the following events occurs:

1.

Hardware reset.

2.

The receiver is soft reset.

3.

The LSR register is read.

Note: This register is intended for read operations only. Writing to this register is not recommended as it may cause indeterminate results.

B0 RXDA – Receiver Data Available.

Set to 1 when the Receiver Holding Register is full.

If the FIFOs are enabled, this bit is set when at least one character is in the RX__FIFO.

Cleared when the CPU reads all the data in the Holding Register or in the RX__FIFO.

B1

UART, Sharp-IR, SIR, CEIR Modes

OE – Overrun Error.

This bit is set to 1 as soon as an overrun condition is detected by the receiver.

Cleared upon read.

FIFOs Disabled: An overrun occurs when a new character is completely received into the receiver front-end section and the

CPU has not yet read the previous character in the receiver holding register. The new character is discarded, and the re-

ceiver holding register is not affected.

Bits

B7

B6

B5

B4

B3

B2

B1

B0

Function

ER__INF/

FR__END

TXEMP

TXRDY

BRK/

MAX__LEN

FE/

PHY__ERR

PE/

BAD__CRC

OE

RXDA

Reset State

01

1

0

0

0

0

0

FIGURE 12. Link Status Register

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