PC87108AVHG datasheet(5/56 Pages) NSC

5 / 56 page

1.0 Pin Description (Continued)

Symbol

Pin(s)

Type

Description

BUS INTERFACE SIGNALS

DACK0 , DACK1 ,

DACK3

73, 75, 77

DMA Acknowledge. Active low inputs to acknowledge the corresponding DMA

requests and enable the RD or WR signals during a DMA access cycle.

DRQ0, DRQ1,

DRQ3

72, 74, 76

DMA Request. Active high outputs to signal the DMA controller that a data

transfer from the PC87108A is required.

IRQ3–5, IRQ7,

IRQ9,

IRQ11, IRQ15

62–68

Interrupt Request. These outputs are used to signal an interrupt condition to

the CPU. Only one signal can be selected at any one time, the others are

disabled (Section 4.2.2). The selected IRQ signal can be configured to be either

open-drain or totem-pole. Its polarity is also programmable.

Master Reset. A high level on this input resets the PC87108A. This signal

asynchronously terminates any activity and places the device in the Disable

state. Upon MR deassertion, the BADDR[0–1] inputs are sampled to select the

accessing mode and/or the base address.

Read. Active low input asserted by the CPU or DMA controller to read data or

status information from the PC87108A.

Terminal Count. This input is asserted by the DMA controller to indicate the

end of a DMA transfer. The signal is only effective during a DMA access cycle.

Write. Active low input asserted by the CPU or DMA controller to write data or

control information to the PC87108A.

UART INTERFACE SIGNALS

CTS

Clear to Send. When low, indicates that the MODEM or Data Set is ready to

accept data. The CTS signal is a MODEM status input whose condition can be

tested by reading the MSR register.

DCD

Data Carrier Detect. When low, indicates that the MODEM or Data Set has

detected a carrier. The DCD signal is a MODEM status input whose condition

can be tested by reading the MSR register.

DSR

Data Set Ready. When low, indicates that the MODEM or Data Set is ready to

establish a communications link. The DSR signal is a MODEM status input

whose condition can be tested by reading the MSR register.

DTR /BOUT

Data Terminal Ready or Baud Generator Clock. Dual function pin. DTR is the

normal pin function. It is used to indicate to the MODEM or Data Set that the

device is ready to exchange data. DTR is activated by setting the appropriate

bit in the MCR register to 1. After a Master Reset operation or during Loop

mode, DTR is set to its inactive state. The BOUT function is enabled by the

BTEST bit in the EXCR1 register. When enabled, the baud generator output

clock is driven on this pin.

Ring Indicator. When low, indicates that a telephone ring signal has been

received by the MODEM. The RI signal is a MODEM status input whose

condition can be tested by reading the MSR register.

RTS

Request to Send. When low, this output indicates to the MODEM or Data Set

that the device is ready to send data. RTS is activated by setting the

appropriate bit in the MCR register to 1. After a Master Reset operation or

during Loop mode, RTS is set to its inactive state.

SIN

Serial Data In. This input receives serial data from the communications link.

SOUT

Serial Data Out. This output sends serial data to the communications link. This

signal is set to a Marking state (logic 1) after a Master Reset operation or when

the device is in one of the Infrared communications modes.

PC87108AVHG Datasheet(PDF) 5 Page - National Semiconductor (TI)

PC87108AVHG Datasheet(HTML) 5 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL