PIC24FJ64GA006 datasheet(6/10 Pages) MICROCHIP

6 / 10 page

PIC24FJ128GA010

DS80330A-page 6

28. Module: Output Compare

In PWM mode, the output compare module may

miss a compare event when the current duty cycle

and the OCxRS register is updated with a value of

0x0001. The compare event is only missed the first

time a value of 0x0001 is written to OCxRS and the

PWM output remains low for one PWM period.

Subsequent PWM high and low times occur as

expected.

Work around

If the current OCxRS register value is 0x0000,

avoid writing a value of 0x0001 to OCxRS.

Instead, write a value of 0x0002. In this case, how-

ever, the duty cycle will be slightly different from

the desired value.

Date Codes that pertain to this issue:

All engineering and production devices.

29. Module: RTCC

The RTCC alarm repeat will generate an incorrect

number of pin toggles. If the repeat count (x) is

even, it will toggle the alarm pin ‘x’ times. If the

repeat count is odd, one less than x toggles will be

observed (x – 1).

Work around

None at this time.

Date Codes that pertain to this issue:

All engineering and production devices.

30. Module: RTCC

When performing writes to the ALCFGRPT regis-

ter, some bits may become corrupted. The error

occurs because of desynchronization between the

CPU clock domain and the RTCC clock domain.

The error causes data from the instruction follow-

ing the ALCFGRPT instruction to overwrite the

data in ALCFGRPT.

Work around

Always follow writes to the ALCFGRPT register

with an additional write of the same data to a

dummy location. These writes can be performed to

RAM locations, W registers or unimplemented

SFR space.

The optimal way to perform the work around:

1. Read ALCFGRPT into a RAM location.

2. Modify the ALCFGRPT data, as required, in

RAM.

3. Move the RAM value into ALCFGRPT and a

dummy location in back-to-back instructions.

Date Codes that pertain to this issue:

All engineering and production devices.

31. Module: CRC

If a CRC FIFO overflow occurs, the VWORD indi-

cator will reset to ‘1’ instead of ‘0’. Further writes to

the FIFO will cause the VWORD indicator to reset

to ‘0’ after seven writes are performed.

Work around

Poll the CRCFUL bit (CRCCON<7>) to ensure that

no writes are performed on the FIFO when it is full.

Date Codes that pertain to this issue:

All engineering and production devices.

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