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PIC24FJ64GA006 Datasheet(PDF) 1 Page - Microchip Technology |
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PIC24FJ64GA006 Datasheet(HTML) 1 Page - Microchip Technology |
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1 / 10 page ![]() © 2007 Microchip Technology Inc. DS80330A-page 1 PIC24FJ128GA010 The PIC24FJ128GA010 family Rev. A4 parts you have received conform functionally to the Device Data Sheet (DS39747C), except for the anomalies described below. Any Data Sheet Clarification issues related to the PIC24FJ128GA010 Family will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues. The following silicon errata apply only to PIC24FJ128GA010 devices with these Device/ Revision IDs: 1. Module: Core With Doze mode enabled, DOZEN (CLKDIV<11>) set, and the CPU Peripheral Clock Ratio Select bits (CLKDIV<14:12>) configured to any value except 0b000, writes to SFR locations can not be performed. Work around Disable Doze mode, or select 1:1 CPU peripheral clock ratio before modifying stated SFR locations, or avoid writing stated locations while Doze mode is enabled and CPU peripheral clock ratio other than 1:1 is selected. Configure the device prior to entering Doze mode and use the mode only to monitor applications activity. Date Codes that pertain to this issue: All engineering and production devices. 2. Module: JTAG The current JTAG programming implementation is not compatible with third party programmers using SVF (Serial Vector Format) description language. JTAG boundary scan is supported by third party JTAG solutions and is not affected. Work around Program devices with In-Circuit Serial Programming™. JTAG programming can be accomplished using custom JTAG software. The current implementation may not be supported in future PIC24F revisions. JTAG boundary scan is supported. Date Codes that pertain to this issue: All engineering and production devices. 3 Module: PMP In Master mode (MODE<1:0> = 11 or 10), back- to-back operations may cause the PMRD signal to not be generated. This limitation occurs when the peripheral is configured for zero wait states (WAITM<3:0> = 0000). Work around The PMRD signal will be generated correctly if a minimum of one instruction cycle delay is inserted between the back-to-back operations. A NOP instruction, or any other instruction, is adequate. Selecting a delay other than zero will also permit the PMRD signal to be generated. Date Codes that pertain to this issue: All engineering and production devices. 4. Module: Interrupts The device may not exit Doze mode if certain trap conditions occur. Address error, stack error and math error traps are affected. Oscillator failure and all interrupt sources are not affected and can cause the device to correctly exit Doze mode. Work around None. Date Codes that pertain to this issue: All engineering and production devices. Part Number Device ID Revision ID PIC24FJ128GA010 040Dh 04h PIC24FJ96GA010 040Ch 04h PIC24FJ64GA010 040Bh 04h PIC24FJ128GA008 040Ah 04h PIC24FJ96GA008 0409h 04h PIC24FJ64GA008 0408h 04h PIC24FJ128GA006 0407h 04h PIC24FJ96GA006 0406h 04h PIC24FJ64GA006 0405h 04h The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses in program memory. They are shown in hexadecimal in the format “DEVID DEVREV”. PIC24FJ128GA010 Family Rev. A4 Silicon Errata |
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