ADV7181C

Data Sheet

Rev. E | Page 10 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

64 63 62

61

60 59 58

57 56 55 54 53 52 51 50 49

47

AIN4

46

AIN3

45

NC

42

CML

43

AGND

44

CAPC2

48

AIN5

41

REFOUT

40

AVDD

39

CAPY2

37

AGND

36

AIN2

35

AIN1

34

FB

33

NC

38

CAPY1

2

HS/CS

3

DGND

4

DVDDIO

7

P13

6

P14

5

P15

1

INT

8

P12

9

SFL/SYNC_OUT

10

DGND

12

P11

13

P10

14

P9

15

P8

16

P7

11

DVDDIO

17 18

19

20

21 22 23

24 25 26

27 28 29 30 31 32

PIN 1

ADV7181C

TOP VIEW

(Not to Scale)

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

Figure 6. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

1

INT

O

Interrupt. This pin can be active low or active high. When SDP/CP status bits

change, this pin is triggered. The set of events that triggers an interrupt is

under user control.

2

HS/CS

O

HS: Horizontal Synchronization Output Signal (SDP and CP Modes).

CS: Digital Composite Synchronization Signal (CP Mode).

3, 10, 24, 57

DGND

G

Digital Ground.

4, 11

DVDDIO

P

Digital I/O Supply Voltage (3.3 V).

28 to 25, 19 to 12, 8 to 5,

62 to 59

P0 to P19

O

Video Pixel Output Port. Refer to Table 10 for output configuration modes.

9

SFL/SYNC_OUT

O

SFL: Subcarrier Frequency Lock. This pin contains a serial output stream that

can be used to lock the subcarrier frequency when this decoder is connected

to any Analog Devices digital video encoder.

SYNC_OUT: Sliced Synchronization Output Signal Available Only in CP Mode.

20

LLC

O

Line-Locked Output Clock. This pin is for the pixel data (the range is

12.825 MHz to 110 MHz).

21

XTAL1

O

This pin should be connected to the 28.63636 MHz crystal or left as a no connect

if an external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the

ADV7181C. In crystal mode, the crystal must be a fundamental crystal.

22

XTAL

I

Input pin for 28.63636 MHz crystal, or can be overdriven by an external 3.3 V,

28.63636 MHz clock oscillator source to clock the ADV7181C.

23, 58

DVDD

P

Digital Core Supply Voltage (1.8 V).

29

PWRDWN

I

A Logic 0 on this pin places the ADV7181C in a power-down mode.

30

ELPF

O

The recommended external loop filter must be connected to this ELPF pin.

31

PVDD

P

PLL Supply Voltage (1.8 V).

32, 37, 43

AGND

G

Analog Ground.