Data Sheet

AD7699

Rev. F | Page 9 of 32

AD7699

9

8

7

6

5

4

3

2

1

IN3

IN2

IN0

VIO

A

VDD

VDD

IN1

SDO

B

REF

REFIN

DIN

SCK

C

GND

GND

IN7

CNV

D

IN4

IN5

IN6

COM

E

Figure 5. 20-Lead WLCSP Pin Configuration

Table 7. 20-Lead WLCSP Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

B6, B8

VDD

P

Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with 10 μF and

100 nF capacitors. When using the internal reference for a 2.5 V output, the minimum must be 3.0 V. When

using the internal reference for 4.096 V output, the minimum must be 4.6 V.

C9

REF

AI/O

Reference Input/Output. See the Voltage Reference Output/Input section. When the internal reference is

enabled, this pin produces a selectable system reference of 2.5 V or 4.096 V. When the internal reference is

disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin

(VDD − 0.5 V, maximum), which is useful when using low cost, low power references. For improved drift

performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs

decoupling with an external 10 μF capacitor connected as close to REF as possible. See the Reference

Decoupling section.

C7

REFIN

AI/O

Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section. When

using the internal reference, the internal unbuffered reference voltage is present and requires decoupling with

a 0.1 μF capacitor. When using the internal reference buffer, apply a source between 0.5 V and (VDD − 0.5 V) that

is buffered to the REF pin, as described in the REF pin description.

D6, D8

GND

P

Power Supply Ground.

A7

IN3

AI

Analog Input Channel 3.

E5

IN5

AI

Analog Input Channel 5.

E3

IN6

AI

Analog Input Channel 6 .

D4

IN7

AI

Analog Input Channel 7.

E1

COM

AI

Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode point of 0 V or VREF/2 V.

D2

CNV

DI

Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held low, the

busy indictor is enabled.

C5

DIN

DI

Data Input. Use this input for writing to the 14-bit configuration register. The configuration register can be

written to during and after conversion.

C3

SCK

DI

Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first

fashion.

B2

SDO

DO

Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar modes,

conversion results are straight binary; in bipolar modes, conversion results are twos complement.

A1

VIO

P

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).

A3

IN0

AI

Analog Input Channel 0.

B4

IN1

AI

Analog Input Channel 1.

A5

IN2

AI

Analog Input Channel 2.

E7

IN4

AI

Analog Input Channel 4 .

1

AI means analog input, AI/O means analog input/output, DI means digital input, DO means digital output, P means power, and NC means no internal connection.