M2006-02A Datasheet Rev 1.0

4 of 8

Revised 28Jul2004

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Integrated

Circuit

Systems, Inc.

M2006-02A

Prod uct Data Sh eet

The PLL

The PLL uses a phase detector and configurable

dividers to synchronize the output of the VCSO with

selected reference clock.

The “Mfin Divider” and “Mfec Divider” divide the VCSO

frequency, feeding the result into the phase detector.

The selected input reference clock is divided by the

“Rfec Divider”. The result is fed into the other input of

the phase detector.

The phase detector compares its two inputs. It then

outputs pulses to the loop filter as needed to increase or

decrease the VCSO frequency and thereby match and

lock the divider output’s frequency and phase to those

of the input reference clock.

Due to the narrow tuning range of the VCSO

(+200ppm), appropriate selection of all of the following

are required for the PLL be able to lock: VCSO center

frequency, input frequency, and divider selections.

Maintaining PLL Lock:

The narrow tuning range of the VCSO requires that the

input reference frequency must remain suitable for the

current look-up table selection. For example, when

switching between “Inverse FEC ratio” and “Non-FEC

ratio” look-up table selections (see Table 5 on pg. 3), the

input reference frequency must change accordingly in

order for the PLL to lock.

An out-of-lock condition due to an inappropriate

configuration will typically result in the VCSO

operating at its lower or upper frequency rail,

which is approximately 200ppm above or below

the nominal VCSO center frequency.

Relationship Among Frequencies and Dividers

The VCSO center frequency must be specified at time

of order. The relationship between the VCSO (Fvcso)

frequency, the Mfin divider, the Mfec divider, the Rfec

divider, and the input reference frequency (Fin) is:

and inverse-FEC PLL ratios in Table 5 enable use with

these corresponding input reference frequencies:

Outputs

The M2006-02A provides a total of two differential

FOUT0

can output the two different frequencies at the

Any unused output should be left unconnected

(floating) in the system application. This will

minimize output switching current and therefore

minimize noise modulation of the VCSO.

M2006-02A-622.0800

M2006-02A-622.0800

VCSO Clock

Frequency (MHz)

FEC Ratio

=

Base Input Ref.

Note 1: Input reference clock (“Fin”) can be the base frequency

shown divided by “Mfin” (as shown in Table 4 on pg. 3).

622.08

1

/

1

622.0800

238

/ 255

666.5143

237

/ 255

669.3266

236

/ 255

672.1627

Table 7: Example FEC PLL Rations and Input Reference Frequencies

Fvcso

Fin

Mfin

×

Mfec

Rfec

--------------

×

=

÷